Abstract: An input analog signal is sampled at a sampling frequency f.sub.s, which is four times a carrier frequency f.sub.c. A demultiplexer 11 outputs supplied data to four systems sequentially, and generates four zero carriers whose frequencies and amplitudes are equal to each other, with only the phases being different. The delay circuits 12 to 15 delay each one of the zero carriers, and supply delayed signals to adaptive filters 16 to 19. Data output from the four adaptive filters 16 to 19 are selected by a multiplexer 22, and the multiplexer 22 outputs the selected signals as a single signal. The difference between a first zero carrier and an output signals of the first adaptive filter 16 is obtained, and tap coefficients of the adaptive filters 16 to 19 are controlled in accordance with an LMS algorithm based on the difference. A signal output by the multiplexer 22 is output as a reproduced carrier.

Abstract: A semiconductor memory device is constituted such that, when a first wiring layer provides a bit line of a first common complementary data line pair and a third wiring layer provides a bit line of a second common complementary data line pair, a second wiring layer makes an overlapped area between the bit line and the bit bar line of the second common complementary dada line pair equal to the bit line of the first common complementary data line pair and also an overlapped area between the bit line and the bit bar line of the first common complementary data line pair equal to the bit line of the second common complementary data line pair.

Abstract: A semiconductor memory device includes memory elements, each maintaining memory contents within a period of time during which a refresh operation is repeated, and a refresh request circuit for making a refresh request. The semiconductor memory device includes refreshing circuits each of which, in response to a refresh request from the refresh request circuit, performs a refresh operation on a different number of memory elements at the same time, and a selecting circuit for selecting one refreshing circuit from among the refreshing circuits according to the number of memory elements included in the semiconductor memory device. The refresh request circuit can change the interval at which it makes a refresh request.

Abstract: Constants {P.sub.b00i, Q.sub.b00j, . . . , P.sub.ak2i, Q.sub.ak2j, P.sub.ci, Q.sub.cj, P.sub.di, and Q.sub.dj } for calculating each of filter coefficients {a.sub.k1, a.sub.k2, b.sub.00, b.sub.k1, b.sub.k2, c and d} for a digital filter 15 by using non-linear polynomials for pass band position data x and pass band width data y are stored in a memory 13. The constants {P.sub.b00i, Q.sub.b00j, . . . , P.sub.ak2i, Q.sub.ak2j, P.sub.ci, Q.sub.cj, P.sub.di, and Q.sub.dj } are determined by using the least square method so that the sum of the square of the errors between the filter coefficients calculated by using non-liner polynomials and the filter coefficients of digital filter having known characteristics becomes the least or the minimum. A CPU 11 calculates the filter coefficients non-linearly by using the constants stored in the memory 13, and sets the results to the digital filter 15 when new pass band position data x or pass band width data y is input at knobs SC and SW.

Abstract: Data from an A/D converter is supplied to a fixed-point DSP. The fixed-point DSP adjusts the level of the data x so that computed results do not exceed .+-.1. In succession, for the i-th data x.sub.i, the fixed-point DSP computes cos .pi..multidot.x.sub.i when i=1, 5, . . . , -sin .pi..multidot.x.sub.i when i=2, 6, . . . , -cos .pi..multidot.x.sub.i when i=3, 7, . . . and sin .pi..multidot.x.sub.i when i=4, 8, . . . and outputs a digital phase modulated signal y(t) by outputting the computed results in order. Trigonometrical functions are computed by expanding them to a series so that the intermediate computed results do not exceed .+-.1.

Abstract: A disk drive apparatus and read error recovery method in a disk drive apparatus removes thermal asperities on disk surfaces. A projection, such as a thermal asperity, on the recording surfaces of disks is detected when a signal transducer head contacts the projection. The flying height of the signal transducer head is lowered, e.g., by changing the disk rotation speed from the normal rotation speed in read/write operations or by heating a suspension having a bimetal element, while the signal transducer head is positioned over the detected projection on the track. The signal transducer head strikes the projection to break the projection. This avoids a subsequent error from being caused by the thermal asperity.

Abstract: A disk drive apparatus and read error recovery method in a disk drive apparatus removes thermal asperities on disk surfaces. A projection, such as a thermal asperity, on the recording surfaces of disks is detected when a signal transducer contacts the projection. The flying height of the signal transducer is lowered, e.g., by reducing the disk rotation speed from the normal rotation speed in read/write operations, while the signal transducer is positioned over the detected projection on the track. The signal transducer strikes the projection to break the projection. This avoids a subsequent error from being caused by the thermal asperity.

Abstract: A smaller, high-speed, semiconductor memory device having redundancy is disclosed which attains an improved mass productivity. Where a main memory (20) includes a defective memory cell, a defective address designating circuit (21) stores the address of the defective memory cell. Defective address detecting circuits (22a to 22r) detect whether an address signal received at an address signal input terminal (4) coincides with an address signal from the defective address designating circuit (21). If a signal indicative of the coincidence is given to a redundancy memory circuit (23) from the defective address detecting circuits (22a to 22r), data is written in or read from defective address remedy latch circuit groups (23a to 23r) of the redundancy memory circuit (23) which correspond to the defective address detecting circuits (22a to 22r). A data selector (24) selectively outputs data received from the defective address remedy latch circuit groups (23a to 23r) or data received from the main memory (20).

Abstract: In order to obtain a redundancy circuit which can freely arrange its fuse in a required position with disciplined accessibility after employment, a combination circuit (50) receives outputs (QA0 to QA7) obtained by decoding a column address (AXM) by a column line decoder (2), signals (QB0 to QB7) indicating a faulty line, signals (L0 to L7) generated from the signals (QB0 to QB7) and an inverted signal (ENB*), to generate signals (YS0 to YS8) for controlling selecting switches for specifying column lines. If a K-th column line is faulty, a column line selecting switch for selecting the K-th column line is forcibly turned off and an (N+1)-th column line is allocated with respect to specification of an N-th column line (N.gtoreq.K). Thus, fuse positions of redundancy circuits can be standarlized between products so that the products can be easily mass-produced and supplied at a low cost even if the redundancy circuits are contained in small quantities of various ASICs.

Abstract: A serial selection circuit is disclosed for sequentially selecting a word line in a semiconductor memory. Flipflops (latch circuits) for respectively holding the state are connected to each word line W0 to W1023. These flipflops are sequentially activated in response to two-phase non-overlap clock signals, and then deactivated. This serial selection circuit has the circuit structure being highly simplified compared with the conventional row decoder, so that the occupied area on the semiconductor chip is substantially reduced.