Patents by Inventor Michio Sono

Michio Sono has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6528346
    Abstract: First and second ball forming plates are prepared. The cavities of the first plate and the cavities of the second plate 20 are filled with solder paste, respectively. The first plate and the second plate are placed in a facing relationship to each other and heated to form metal balls each of which corresponds to the total metal components of the solder paste in one cavity of the first plate and one cavity in the second plate. The metal balls are formed in the cavities of the lower plate 10. The metal balls are transferred from the cavities of the first plate to a device on which bumps are to be formed.
    Type: Grant
    Filed: December 28, 2000
    Date of Patent: March 4, 2003
    Assignee: Fujitsu Limited
    Inventors: Masayuki Ochiai, Hidefumi Ueda, Michio Sono, Ichiro Yamaguchi, Kazuhiko Mitobe, Koki Otake, Junichi Kasai, Nobuo Kamehara, Yasuo Yamagishi, Masataka Mizukoshi
  • Publication number: 20010018263
    Abstract: First and second ball forming plates are prepared. The cavities of the first plate and the cavities of the second plate 20 are filled with solder paste, respectively. The first plate and the second plate are placed in a facing relationship to each other and heated to form metal balls each of which corresponds to the total metal components of the solder paste in one cavity of the first plate and one cavity in the second plate. The metal balls are formed in the cavities of the lower plate 10. The metal balls are transferred from the cavities of the first plate to a device on which bumps are to be formed.
    Type: Application
    Filed: December 28, 2000
    Publication date: August 30, 2001
    Inventors: Masayuki Ochiai, Hidefumi Ueda, Michio Sono, Ichiro Yamaguchi, Kazuhiko Mitobe, Koki Otake, Junichi Kasai, Nobuo Kamehara, Yasuo Yamagishi, Masataka Mizukoshi
  • Patent number: 6025258
    Abstract: A method for fabricating solder bumps onto a semiconductor chip. A solder ball forming member having a flat surface and a plurality of cavities arranged on the flat surface in a predetermined pattern is prepared. The cavities are then filled with a solder paste, and the solder ball forming member is heated to a temperature higher than the melting point of the solder so that the molten solder powder in the solder paste form solder balls due to surface tension. The semiconductor chip is then moved toward the solder ball forming member to transfer the heated solder balls from the solder ball forming member to the semiconductor chip.
    Type: Grant
    Filed: August 17, 1995
    Date of Patent: February 15, 2000
    Assignee: Fujitsu Limited
    Inventors: Masayuki Ochiai, Hidefumi Ueda, Michio Sono, Ichiro Yamaguchi, Kazuhiko Mitobe, Koki Otake, Junichi Kasai, Nobuo Kamehara, Yasuo Yamagishi, Masataka Mizukoshi
  • Patent number: 6022759
    Abstract: A semiconductor device includes a semiconductor element, a semiconductor device base member having an element mounting portion on which the semiconductor element is mounted, external connection terminals provided on the semiconductor device base member and electrically connected to the semiconductor element, and a resin sealing the semiconductor element. The semiconductor device base member includes a base part and lead parts supported by the base part. The lead parts are electrically connected to the external connection terminals. The semiconductor device base member has bent portions in which the lead parts are located on outer sides of the semiconductor device base member. The bent portions are located in edge portions of the semiconductor device base member.
    Type: Grant
    Filed: February 18, 1998
    Date of Patent: February 8, 2000
    Assignees: Fujitsu Limited, Fujitsu Automation Limited
    Inventors: Masaaki Seki, Michio Sono, Ichiro Yamaguchi, Kazuhiko Mitobe, Lim Cheang Hai, Koki Otake, Susumu Abe, Junichi Kasai, Masao Sakuma, Yoshimi Suzuki, Yasuhiro Shinma
  • Patent number: 5920117
    Abstract: A semiconductor device includes a board having a lower surface, a container part created in the board, external-connection nodes provided on the lower surface of the board, a supporting member provided inside the container part and secured by the board, a semiconductor chip secured on the supporting member and electrically connected with the external-connection nodes, and a sealing resin fully filling the container part so as to completely cover the semiconductor chip.
    Type: Grant
    Filed: March 18, 1997
    Date of Patent: July 6, 1999
    Assignee: Fujitsu Limited
    Inventors: Michio Sono, Masashi Takenaka, Masanori Yoshimoto, Tsuyoshi Aoki, Ichiro Yamaguchi, Koki Otake
  • Patent number: 5861669
    Abstract: A semiconductor device having a package of a single in-line type includes a semiconductor chip, a package body that accommodates the semiconductor chip therein and defined by a pair of opposing major surfaces and a plurality of interconnection leads held by the package body to extend substantially perpendicularly to a bottom surface. Each of the interconnection leads consists of an inner lead part located inside the package body and an outer lead part located outside the package body, the outer lead part being bent laterally at a boundary between the inner part and the outer part, in one of first and second directions that are opposite from each other and substantially perpendicular to the opposing major surfaces of the package body. A plurality of support legs extend laterally at the bottom surface of the package body for supporting the package body upright when the semiconductor device is placed on a substrate.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: January 19, 1999
    Assignee: Fujitsu Limited
    Inventors: Michio Sono, Junichi Kasai, Masanori Yoshimoto, Kazuto Tsuji, Kouji Saito
  • Patent number: 5831332
    Abstract: A semiconductor device having a package of a single in-line type includes a semiconductor chip, a package body that accommodates the semiconductor chip therein and defined by a pair of opposing major surfaces and a plurality of interconnection leads held by the package body to extend substantially perpendicularly to a bottom surface. Each of the interconnection leads consists of an inner lead part located inside the package body and an outer lead part located outside the package body, the outer lead part being bent laterally at a boundary between the inner part and the outer part, in one of first and second directions that are opposite from each other and substantially perpendicular to the opposing major surfaces of the package body. A plurality of support legs extend laterally at the bottom surface of the package body for supporting the package body upright when the semiconductor device is placed on a substrate.
    Type: Grant
    Filed: October 29, 1996
    Date of Patent: November 3, 1998
    Assignee: Fujitsu Limited
    Inventors: Michio Sono, Junichi Kasai, Masanori Yoshimoto, Kazuto Tsuji, Kouji Saito
  • Patent number: 5804468
    Abstract: A process for manufacturing semiconductor device having a package in which a semiconductor device is sealed includes a base, and a metallic film is formed on a surface of the base. The semiconductor chip is formed on the metallic film. A pad formed on the semiconductor chip is connected to the metallic film by a wire. A sealing layer is formed on the metallic film. Leads are formed on the glass layer. A connecting layer is formed on the metallic film and contains electrically conductive particles. The connecting layer is in contact with a lead for a power supply system and connecting the metallic film to the lead.
    Type: Grant
    Filed: November 21, 1995
    Date of Patent: September 8, 1998
    Assignees: Fujitsu Limited, Kyushu Fujitsu Electronics Limited
    Inventors: Kazuto Tsuji, Yoshiyuki Yoneda, Hideharu Sakoda, Michio Sono, Ichiro Yamaguchi, Toshio Hamano, Yoshihiro Kubota, Michio Hayakawa, Yoshihiko Ikemoto, Yukio Saigo, Naomi Miyaji
  • Patent number: 5801439
    Abstract: A semiconductor device includes a semiconductor element, a package sealing the semiconductor element, and leads for passing signals between the semiconductor element and an external device. Each of the leads has an inner-lead part sealed within the package and connected with the semiconductor element, and an outer-lead part which extends outward from the package toward a top of the package, and is to be connected to the external device. The outer-lead part includes a first-port part at a lower side of the package, and a second-port part at an upper side of the package.
    Type: Grant
    Filed: February 21, 1997
    Date of Patent: September 1, 1998
    Assignee: Fujitsu Limited
    Inventors: Tetsuya Fujisawa, Mitsutaka Sato, Junichi Kasai, Masataka Mizukoshi, Kosuke Otokita, Hiroshi Yoshimura, Katsuhiro Hayashida, Akira Takashima, Masahiko Ishiguri, Michio Sono
  • Patent number: 5786985
    Abstract: A semiconductor device is adapted to be mounted on a circuit substrate in an approximate vertical position. The semiconductor device includes a semiconductor chip, a stage having a first surface and a second surface opposite to the first surface, where the semiconductor chip is mounted on the first surface, a resin package encapsulating the semiconductor chip, where the resin package has upper and lower surfaces and side surfaces, a plurality of leads respectively having one end electrically connected to the semiconductor chip and another end extending downwardly from the lower surface of the resin package, and an upper extension, provided on the stage, extending upwardly from the upper surface of the resin package.
    Type: Grant
    Filed: November 15, 1996
    Date of Patent: July 28, 1998
    Assignee: Fujitsu Limited
    Inventors: Norio Taniguchi, Junichi Kasai, Kazuto Tsuji, Michio Sono, Masanori Yoshimoto, Katsuhiro Hayashida, Mitsutaka Sato, Hiroshi Yoshimura, Tadashi Uno, Kosuke Otokita, Tetsuya Fujisawa
  • Patent number: 5760471
    Abstract: A semiconductor device including a semiconductor element, and leads connected with the semiconductor element. Each of the leads includes an outer lead part for being connected externally. The semiconductor device further includes a plastic package sealing the semiconductor element and the leads. In the semiconductor device, the outer lead part is exposed to the outside of a side face of the plastic package, and the plastic package is mounted on any base in a standing form by the side face contacting the base.
    Type: Grant
    Filed: February 3, 1997
    Date of Patent: June 2, 1998
    Assignee: Fujitsu Limited
    Inventors: Tetsuya Fujisawa, Mitsutaka Sato, Junichi Kasai, Masataka Mizukoshi, Kousuke Otokita, Hiroshi Yoshimura, Katsuhiro Hayashida, Akira Takashima, Masahiko Ishiguri, Michio Sono
  • Patent number: 5747874
    Abstract: A semiconductor device includes a semiconductor element, a semiconductor device base member having an element mounting portion on which the semiconductor element is mounted, external connection terminals provided on the semiconductor device base member and electrically connected to the semiconductor element, and a resin sealing the semiconductor element. The semiconductor device base member includes a base part and lead parts supported by the base part. The lead parts are electrically connected to the external connection terminals. The semiconductor device base member has bent portions in which the lead parts are located on outer sides of the semiconductor device base member. The bent portions are located in edge portions of the semiconductor device base member.
    Type: Grant
    Filed: September 18, 1995
    Date of Patent: May 5, 1998
    Assignees: Fujitsu Limited, Fujitsu Automation Limited
    Inventors: Masaaki Seki, Michio Sono, Ichiro Yamaguchi, Kazuhiko Mitobe, Lim Cheang Hai, Koki Otake, Susumu Abe, Junichi Kasai, Masao Sakuma, Yoshimi Suzuki, Yasuhiro Shinma
  • Patent number: 5703398
    Abstract: A semiconductor integrated circuit device includes a semiconductor chip supported by a stage, leads electrically connected to the semiconductor chip, first and second heat radiating members provided on first and second sides of the semiconductor chip, and a resin package body completely sealing the semiconductor chip and partially sealing the leads and the first and second heat radiating members.
    Type: Grant
    Filed: June 20, 1996
    Date of Patent: December 30, 1997
    Assignee: Fujitsu Limited
    Inventors: Michio Sono, Kazuto Tsuji, Hideharu Sakoda, Yoshimi Suzuki, Masao Sakuma
  • Patent number: 5684675
    Abstract: A semiconductor device unit includes a holder having a plurality of holding parts, and a plurality of semiconductor devices held by the holding parts of the holder. Each of the semiconductor devices has a generally parallelepiped shape with top and bottom surfaces and at least one side surface provided with leads which are exposed whereby the semiconductor device unit stands by itself on the leads.
    Type: Grant
    Filed: June 1, 1994
    Date of Patent: November 4, 1997
    Assignee: Fujitsu, Ltd.
    Inventors: Norio Taniguchi, Junichi Kasai, Kazuto Tsuji, Michio Sono, Masanori Yoshimoto
  • Patent number: 5659200
    Abstract: A method of producing a semiconductor device includes the steps of fitting a bottom part of a radiator block within a tapered hole which is provided at a bottom of a recess of a jig and positioning on the jig a lead frame having inner and outer leads and wherein the lead frame has an opening at a central part thereof, the opening being located above a top surface of the radiator block. The semiconductor chip is then mounted on the top surface part of the radiator block and bonded to the lead frame by plurality of wires.
    Type: Grant
    Filed: April 13, 1995
    Date of Patent: August 19, 1997
    Assignee: Fujitsu, Ltd.
    Inventors: Michio Sono, Kouji Saito, Masashi Takenaka, Masanori Yoshimoto
  • Patent number: 5643831
    Abstract: A method for fabricating a semiconductor device using a solder ball forming plate having cavities. The plate is made from a silicon plate having a flat surface in a <110> crystallographic plane, and an orientation flat in a <1-11> crystallographic plane. The cavities are formed on the flat surface of the plate by etching, using a mask having openings in the shape of rhombus arranged such that one side of the rhombus is generally parallel to the <1-11> crystallographic plane. As a result, the cavities having wedge-shaped bottom are formed. The cavities are then filled with a solder paste and are heated to form solder balls in the cavities while the plate in an inclined position. The solder balls are then transferred from the plate to a semiconductor chip.
    Type: Grant
    Filed: October 24, 1995
    Date of Patent: July 1, 1997
    Assignee: Fujitsu Limited
    Inventors: Masayuki Ochiai, Hidefumi Ueda, Michio Sono, Ichiro Yamaguchi, Kazuhiko Mitobe, Koki Otake, Junichi Kasai, Nobuo Kamehara, Yasuo Yamagishi, Masataka Mizukoshi, Yutaka Yamada, Susumu Abe
  • Patent number: 5574310
    Abstract: A semiconductor device having a package of a single in-line type includes a semiconductor chip, a package body that accommodates the semiconductor chip therein and defined by a pair of opposing major surfaces and a plurality of interconnection leads held by the package body to extend substantially perpendicularly to a bottom surface. Each of the interconnection leads consists of an inner lead part located inside the package body and an outer lead part located outside the package body, the outer lead part being bent laterally at a boundary between the inner part and the outer part, in one of first and second directions that are opposite from each other and substantially perpendicular to the opposing major surfaces of the package body. A plurality of support legs extend laterally at the bottom surface of the package body for supporting the package body upright when the semiconductor device is placed on a substrate.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: November 12, 1996
    Assignee: Fujitsu Limited
    Inventors: Michio Sono, Junichi Kasai, Masanori Yoshimoto, Kazuto Tsuji, Kouji Saito
  • Patent number: 5521432
    Abstract: A semiconductor device includes a semiconductor chip, a die-pad on which the semiconductor chip is mounted, a package encapsulating the die pad and the semiconductor chip, and a plurality of leads electrically connected to the semiconductor chip and projecting from the package, wherein each of the leads has a lead body made of pure nickel (Ni) having a purity equal to or greater than 99% and a first film formed thereon, the first film being made of palladium (Pd).
    Type: Grant
    Filed: June 1, 1994
    Date of Patent: May 28, 1996
    Assignee: Fujitsu Limited
    Inventors: Kazuto Tsuji, Yoshiyuki Yoneda, Junichi Kasai, Michio Sono
  • Patent number: 5497032
    Abstract: A semiconductor device having a package in which a semiconductor device is sealed includes a base, and a metallic film is formed on a surface of the base. The semiconductor chip is formed on the metallic film. A pad formed on the semiconductor chip is connected to the metallic film by a wire. A sealing layer is formed on the metallic film. Leads are formed on the glass layer. A connecting layer is formed on the metallic film and contains electrically conductive particles. The connecting layer is in contact with a lead for a power supply system and connecting the metallic film to the lead.
    Type: Grant
    Filed: March 16, 1994
    Date of Patent: March 5, 1996
    Assignees: Fujitsu Limited, Kyushu Fujitsu Electronics Limited
    Inventors: Kazuto Tsuji, Yoshiyuki Yoneda, Hideharu Sakoda, Michio Sono, Ichiro Yamaguchi, Toshio Hamano, Yoshihiro Kubota, Michio Hayakawa, Yoshihiko Ikemoto, Yukio Saigo, Naomi Miyaji
  • Patent number: 5451815
    Abstract: A semiconductor device includes vertical placement part for mounting the semiconductor device on a surface of a circuit board in a vertical position, and a connection part for making electrical connections between the circuit board and a semiconductor element. A stage is provided on which the semiconductor element is placed. The stage has supporting members causing the semiconductor device to vertically stand on the circuit board. Wiring boards, stacked on a side of the stage on which the semiconductor element is placed, have windows in which the semiconductor element is located. The vertical placement part includes wiring lines extending between edges of the wiring boards facing the circuit board and peripheries of the windows. The wiring lines have ends located in the vicinity of the edges of the wiring boards and have a shape enabling the semiconductor device to be mounted on the circuit board.
    Type: Grant
    Filed: March 22, 1994
    Date of Patent: September 19, 1995
    Assignee: Fujitsu Limited
    Inventors: Norio Taniguchi, Kazuto Tsuji, Junichi Kasai, Michio Sono