Patents by Inventor Michiru Hogyoku
Michiru Hogyoku has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240008278Abstract: A semiconductor memory device according to an embodiment includes a first stacked body, a second stacked body, an intermediate conductive layer, an intermediate insulating layer, a semiconductor pillar, a charge storage film, and an insulating film. The semiconductor pillar includes a first part, a second part, and a third part. The charge storage film includes a first charge storage portion and a second charge storage portion. The charge storage film includes at least one first element selected from the group consisting of nitrogen, hafnium, and aluminum. The insulating film provides in at least a portion between the intermediate conductive layer and the first part. The insulating film not includes the first element, or the insulating film has a concentration of the first element lower than a concentration of the first element of the charge storage film.Type: ApplicationFiled: July 26, 2023Publication date: January 4, 2024Applicant: KIOXIA CORPORATIONInventors: Hiroki TOKUHIRA, Takahisa KANEMURA, Shigeo KONDO, Michiru HOGYOKU
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Patent number: 11751399Abstract: A semiconductor memory device according to an embodiment includes a first stacked body, a second stacked body, an intermediate conductive layer, an intermediate insulating layer, a semiconductor pillar, a charge storage film, and an insulating film. The semiconductor pillar includes a first part, a second part, and a third part. The charge storage film includes a first charge storage portion and a second charge storage portion. The charge storage film includes at least one first element selected from the group consisting of nitrogen, hafnium, and aluminum. The insulating film provides in at least a portion between the intermediate conductive layer and the first part. The insulating film not includes the first element, or the insulating film has a concentration of the first element lower than a concentration of the first element of the charge storage film.Type: GrantFiled: April 8, 2022Date of Patent: September 5, 2023Assignee: KIOXIA CORPORATIONInventors: Hiroki Tokuhira, Takahisa Kanemura, Shigeo Kondo, Michiru Hogyoku
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Publication number: 20220231032Abstract: A semiconductor memory device according to an embodiment includes a first stacked body, a second stacked body, an intermediate conductive layer, an intermediate insulating layer, a semiconductor pillar, a charge storage film, and an insulating film. The semiconductor pillar includes a first part, a second part, and a third part. The charge storage film includes a first charge storage portion and a second charge storage portion. The charge storage film includes at least one first element selected from the group consisting of nitrogen, hafnium, and aluminum. The insulating film provides in at least a portion between the intermediate conductive layer and the first part. The insulating film not includes the first element, or the insulating film has a concentration of the first element lower than a concentration of the first element of the charge storage film.Type: ApplicationFiled: April 8, 2022Publication date: July 21, 2022Applicant: KIOXIA CORPORATIONInventors: Hiroki TOKUHIRA, Takahisa KANEMURA, Shigeo KONDO, Michiru HOGYOKU
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Patent number: 11329060Abstract: A semiconductor memory device according to an embodiment includes a first stacked body, a second stacked body, an intermediate conductive layer, an intermediate insulating layer, a semiconductor pillar, a charge storage film, and an insulating film. The semiconductor pillar includes a first part, a second part, and a third part. The charge storage film includes a first charge storage portion and a second charge storage portion. The charge storage film includes at least one first element selected from the group consisting of nitrogen, hafnium, and aluminum. The insulating film provides in at least a portion between the intermediate conductive layer and the first part. The insulating film not includes the first element, or the insulating film has a concentration of the first element lower than a concentration of the first element of the charge storage film.Type: GrantFiled: September 22, 2020Date of Patent: May 10, 2022Assignee: KIOXIA CORPORATIONInventors: Hiroki Tokuhira, Takahisa Kanemura, Shigeo Kondo, Michiru Hogyoku
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Patent number: 10930660Abstract: A semiconductor memory device according to an embodiment includes a first stacked body, a second stacked body, an intermediate conductive layer, an intermediate insulating layer, a semiconductor pillar, a charge storage film, and an insulating film. The semiconductor pillar includes a first part, a second part, and a third part. The charge storage film includes a first charge storage portion and a second charge storage portion. The charge storage film includes at least one first element selected from the group consisting of nitrogen, hafnium, and aluminum. The insulating film provides in at least a portion between the intermediate conductive layer and the first part. The insulating film not includes the first element, or the insulating film has a concentration of the first element lower than a concentration of the first element of the charge storage film.Type: GrantFiled: February 18, 2020Date of Patent: February 23, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Hiroki Tokuhira, Takahisa Kanemura, Shigeo Kondo, Michiru Hogyoku
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Publication number: 20210005616Abstract: A semiconductor memory device according to an embodiment includes a first stacked body, a second stacked body, an intermediate conductive layer, an intermediate insulating layer, a semiconductor pillar, a charge storage film, and an insulating film. The semiconductor pillar includes a first part, a second part, and a third part. The charge storage film includes a first charge storage portion and a second charge storage portion. The charge storage film includes at least one first element selected from the group consisting of nitrogen, hafnium, and aluminum. The insulating film provides in at least a portion between the intermediate conductive layer and the first part. The insulating film not includes the first element, or the insulating film has a concentration of the first element lower than a concentration of the first element of the charge storage film.Type: ApplicationFiled: September 22, 2020Publication date: January 7, 2021Applicant: TOSHIBA MEMORY CORPORATIONInventors: Hiroki TOKUHIRA, Takahisa KANEMURA, Shigeo KONDO, Michiru HOGYOKU
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Publication number: 20200185395Abstract: A semiconductor memory device according to an embodiment includes a first stacked body, a second stacked body, an intermediate conductive layer, an intermediate insulating layer, a semiconductor pillar, a charge storage film, and an insulating film. The semiconductor pillar includes a first part, a second part, and a third part. The charge storage film includes a first charge storage portion and a second charge storage portion. The charge storage film includes at least one first element selected from the group consisting of nitrogen, hafnium, and aluminum. The insulating film provides in at least a portion between the intermediate conductive layer and the first part. The insulating film not includes the first element, or the insulating film has a concentration of the first element lower than a concentration of the first element of the charge storage film.Type: ApplicationFiled: February 18, 2020Publication date: June 11, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventors: Hiroki TOKUHIRA, Takahisa KANEMURA, Shigeo KONDO, Michiru HOGYOKU
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Patent number: 10608007Abstract: A semiconductor memory device according to an embodiment includes a first stacked body, a second stacked body, an intermediate conductive layer, an intermediate insulating layer, a semiconductor pillar, a charge storage film, and an insulating film. The semiconductor pillar includes a first part, a second part, and a third part. The charge storage film includes a first charge storage portion and a second charge storage portion. The charge storage film includes at least one first element selected from the group consisting of nitrogen, hafnium, and aluminum. The insulating film provides in at least a portion between the intermediate conductive layer and the first part. The insulating film not includes the first element, or the insulating film has a concentration of the first element lower than a concentration of the first element of the charge storage film.Type: GrantFiled: July 15, 2019Date of Patent: March 31, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Hiroki Tokuhira, Takahisa Kanemura, Shigeo Kondo, Michiru Hogyoku
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Publication number: 20190341391Abstract: A semiconductor memory device according to an embodiment includes a first stacked body, a second stacked body, an intermediate conductive layer, an intermediate insulating layer, a semiconductor pillar, a charge storage film, and an insulating film. The semiconductor pillar includes a first part, a second part, and a third part. The charge storage film includes a first charge storage portion and a second charge storage portion. The charge storage film includes at least one first element selected from the group consisting of nitrogen, hafnium, and aluminum. The insulating film provides in at least a portion between the intermediate conductive layer and the first part. The insulating film not includes the first element, or the insulating film has a concentration of the first element lower than a concentration of the first element of the charge storage film.Type: ApplicationFiled: July 15, 2019Publication date: November 7, 2019Applicant: TOSHIBA MEMORY CORPORATIONInventors: Hiroki TOKUHIRA, Takahisa KANEMURA, Shigeo KONDO, Michiru HOGYOKU
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Patent number: 10431590Abstract: A semiconductor memory device according to an embodiment includes a first stacked body, a second stacked body, an intermediate conductive layer, an intermediate insulating layer, a semiconductor pillar, a charge storage film, and an insulating film. The semiconductor pillar includes a first part, a second part, and a third part. The charge storage film includes a first charge storage portion and a second charge storage portion. The charge storage film includes at least one first element selected from the group consisting of nitrogen, hafnium, and aluminum. The insulating film provides in at least a portion between the intermediate conductive layer and the first part. The insulating film not includes the first element, or the insulating film has a concentration of the first element lower than a concentration of the first element of the charge storage film.Type: GrantFiled: January 5, 2018Date of Patent: October 1, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Hiroki Tokuhira, Takahisa Kanemura, Shigeo Kondo, Michiru Hogyoku
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Patent number: 9985044Abstract: A semiconductor memory device according to an embodiment, includes a first stacked body, a second stacked body, an intermediate conductive layer, an intermediate insulating layer, a semiconductor pillar, a charge storage film, and an insulating film. The semiconductor pillar includes a first part, a second part, and a third part. The charge storage film includes a first charge storage portion and a second charge storage portion. The charge storage film includes at least one first element selected from the group consisting of nitrogen, hafnium, and aluminum. The insulating film provides in at least a portion between the intermediate conductive layer and the first part. The insulating film not includes the first element, or the insulating film has a concentration of the first element lower than a concentration of the first element of the charge storage film.Type: GrantFiled: September 14, 2016Date of Patent: May 29, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Hiroki Tokuhira, Takahisa Kanemura, Shigeo Kondo, Michiru Hogyoku
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Publication number: 20180130810Abstract: A semiconductor memory device according to an embodiment includes a first stacked body, a second stacked body, an intermediate conductive layer, an intermediate insulating layer, a semiconductor pillar, a charge storage film, and an insulating film. The semiconductor pillar includes a first part, a second part, and a third part. The charge storage film includes a first charge storage portion and a second charge storage portion. The charge storage film includes at least one first element selected from the group consisting of nitrogen, hafnium, and aluminum. The insulating film provides in at least a portion between the intermediate conductive layer and the first part. The insulating film not includes the first element, or the insulating film has a concentration of the first element lower than a concentration of the first element of the charge storage film.Type: ApplicationFiled: January 5, 2018Publication date: May 10, 2018Applicant: TOSHIBA MEMORY CORPORATIONInventors: Hiroki TOKUHIRA, Takahisa KANEMURA, Shigeo KONDO, Michiru HOGYOKU
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Publication number: 20170263614Abstract: A semiconductor memory device according to an embodiment, includes a first stacked body, a second stacked body, an intermediate conductive layer, an intermediate insulating layer, a semiconductor pillar, a charge storage film, and an insulating film. The semiconductor pillar includes a first part, a second part, and a third part. The charge storage film includes a first charge storage portion and a second charge storage portion. The charge storage film includes at least one first element selected from the group consisting of nitrogen, hafnium, and aluminum. The insulating film provides in at least a portion between the intermediate conductive layer and the first part. The insulating film not includes the first element, or the insulating film has a concentration of the first element lower than a concentration of the first element of the charge storage film.Type: ApplicationFiled: September 14, 2016Publication date: September 14, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventors: HIROKI TOKUHIRA, TAKAHISA KANEMURA, SHIGEO KONDO, MICHIRU HOGYOKU
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Publication number: 20160027512Abstract: A nonvolatile semiconductor memory device according to an embodiment includes a control unit, during the read sequence performed to an interested cell, performing a first read operation to detect that a threshold voltage of an adjacent cell is higher than a second reference voltage higher, performing a second read operation to detect that the threshold voltage of the interested cell is higher than a first reference voltage while applying a first bit line voltage to the adjacent bit line when threshold voltages of the adjacent cells are lower than the second reference voltage, and to detect that the threshold voltage of the interested cell is higher than the first reference voltage while applying a second bit line voltage higher than the first bit line voltage to the adjacent bit line when threshold voltages of the adjacent cells are higher than the second reference voltage, after the first read operation.Type: ApplicationFiled: October 27, 2014Publication date: January 28, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Daisuke HAGISHIMA, Mitsutoshi Nakamura, Shigeo Kondo, Michiru Hogyoku
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Patent number: 8503245Abstract: A non-volatile semiconductor memory device according to one aspect of an embodiment of the present invention includes: a semiconductor substrate; an element region; a plurality of memory cell transistors which each include a control gate electrode; and programming means for programming data to a programming target memory cell transistor by applying a programming voltage to the programming target memory cell transistor. Moreover, the programming means applies a programming voltage incremented stepwise from an initial programming voltage, to the programming target memory cell transistor while applying a constant initial intermediate voltage to memory cell transistors adjacent to the programming target memory cell transistor.Type: GrantFiled: March 4, 2011Date of Patent: August 6, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Kunihiro Yamada, Naoyuki Shigyo, Michiru Hogyoku, Hideto Horii
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Publication number: 20110228610Abstract: A non-volatile semiconductor memory device according to one aspect of an embodiment of the present invention includes: a semiconductor substrate; an element region; a plurality of memory cell transistors which each include a control gate electrode; and programming means for programming data to a programming target memory cell transistor by applying a programming voltage to the programming target memory cell transistor. Moreover, the programming means applies a programming voltage incremented stepwise from an initial programming voltage, to the programming target memory cell transistor while applying a constant initial intermediate voltage to memory cell transistors adjacent to the programming target memory cell transistor.Type: ApplicationFiled: March 4, 2011Publication date: September 22, 2011Applicant: Kabushiki Kaisha ToshibaInventors: Kunihiro Yamada, Naoyuki Shigyo, Michiru Hogyoku, Hideto Horii
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Publication number: 20100329026Abstract: According to one embodiment, a semiconductor memory device includes memory cells, first and second selection transistors, a source line, a temperature monitor, and a source line voltage controller. The memory cells are connected in series between a source of the first selection transistor and a drain of the second selection transistor. The temperature monitor monitors a temperature of the semiconductor substrate. The source line voltage controller applies a voltage to the source line, in a read operation, in such a manner that a potential difference between the source line and the semiconductor substrate increases according to a rise in the temperature monitored by the temperature monitor and that a reverse bias is applied between the source of the second selection transistor and the semiconductor substrate.Type: ApplicationFiled: June 24, 2010Publication date: December 30, 2010Inventors: Mitsutoshi NAKAMURA, Takeshi Shimane, Michiru Hogyoku, Katsuaki Isobe, Naoyuki Shigyo
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Patent number: 7093214Abstract: Procedures for SPICE parameter extraction, SPICE calculation, and device simulation for a partially depleted SOI MOSFET are provided. First, SPICE calculation parameters are set. At cthis time, parameters that describe the body current characteristics are not extracted but rather the body current is estimated to be zero. Then, in place of parameters that describe the body current characteristics, information regarding the steady state during circuit operation that is normally found from the body current characteristics, which is to say, the body charge and oscillation in the body potential, is treated as macro parameters that encompass information regarding the body current characteristics. After setting the parameters that include such macro parameters, a SPICE calculation for transient analysis is performed.Type: GrantFiled: November 24, 2003Date of Patent: August 15, 2006Assignee: Seiko Epson CorporationInventor: Michiru Hogyoku
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Publication number: 20050055191Abstract: Procedures for SPICE parameter extraction, SPICE calculation, and device simulation for a partially depleted SOI MOSFET are provided. First, SPICE calculation parameters are set. At this time, parameters that describe the body current characteristics are not extracted but rather the body current is estimated to be zero. Then, in place of parameters that describe the body current characteristics, information regarding the steady state during circuit operation that is normally found from the body current characteristics, which is to say, the body charge and oscillation in the body potential, is treated as macro parameters that encompass information regarding the body current characteristics. After setting the parameters that include such macro parameters, a SPICE calculation for transient analysis is performed.Type: ApplicationFiled: November 24, 2003Publication date: March 10, 2005Inventor: Michiru Hogyoku
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Patent number: 6835982Abstract: A SOI MOSFET 10 may be formed from silicon single crystal as a substrate body that is formed on an embedded oxide film 11. For example, a P-type body 12, a channel section 13, and N-type source region 14 and drain region 15 are formed therein. Low concentration N-type extension regions 18, a gate electrode 17 provided through a gate dielectric layer 16 and sidewalls 19 are formed therein. A body terminal 101 in which a resistance (body resistance) Rb between itself and a body is positively increased is provided, and the body terminal 101 is connected to a source region 14. This structure realizes a SOI MOSFET with a BTS (Body-Tied-to-Source) operation accompanied by a transient capacitive coupling of a body during a circuit operation.Type: GrantFiled: June 27, 2002Date of Patent: December 28, 2004Assignee: Seiko Epson CorporationInventor: Michiru Hogyoku