Patents by Inventor Michiru Hogyoku

Michiru Hogyoku has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6787851
    Abstract: A semiconductor device in accordance with one example of the present invention pertains to a semiconductor device to be used for a CMOS inverter circuit, comprising a BOX layer 2 formed on a silicon substrate 1, a SOI film 3 including single crystal Si formed on the BOX layer, a gate oxide film 4 formed on the SOI film 3, a gate electrode 5 formed on the gate oxide film, and diffusion layers 7, 8 for source/drain regions formed in source/drain regions of the SOI film 3, wherein, when a power supply voltage of 0.6 V is used, a thickness TSOI of the SOI film 3 is 0.084 &mgr;m or greater and 0.094 &mgr;m or smaller, and an impurity concentration of the SOI film is 7.95×1017/cm3 or greater and 8.05×1017/cm3 or smaller.
    Type: Grant
    Filed: December 19, 2001
    Date of Patent: September 7, 2004
    Assignee: Seiko Epson Corporation
    Inventor: Michiru Hogyoku
  • Publication number: 20030025159
    Abstract: A SOI MOSFET 10 may be formed from silicon single crystal as a substrate body that is formed on an embedded oxide film 11. For example, a P-type body 12, a channel section 13, and N-type source region 14 and drain region 15 are formed therein. Low concentration N-type extension regions 18, a gate electrode 17 provided through a gate dielectric layer 16 and sidewalls 19 are formed therein. A body terminal 101 in which a resistance (body resistance) Rb between itself and a body is positively increased is provided, and the body terminal 101 is connected to a source region 14. This structure realizes a SOI MOSFET with a BTS (Body-Tied-to-Source) operation accompanied by a transient capacitive coupling of a body during a circuit operation.
    Type: Application
    Filed: June 27, 2002
    Publication date: February 6, 2003
    Inventor: Michiru Hogyoku
  • Publication number: 20020109192
    Abstract: A semiconductor device in accordance with one example of the present invention pertains to a semiconductor device to be used for a CMOS inverter circuit, comprising a BOX layer 2 formed on a silicon substrate 1, a SOI film 3 comprising single crystal Si formed on the BOX layer, a gate oxide film 4 formed on the SOI film 3, a gate electrode 5 formed on the gate oxide film, and diffusion layers 7, 8 for source/drain regions formed in source/drain regions of the SOI film 3, wherein, when a power supply voltage of 0.6 V is used, a thickness TSOI of the SOI film 3 is 0.084 &mgr;m or greater and 0.094 &mgr;m or smaller, and an impurity concentration of the SOI film is 7.95 x 1017/cm3 or greater and 8.05×1017/ cm3 or smaller.
    Type: Application
    Filed: December 19, 2001
    Publication date: August 15, 2002
    Inventor: Michiru Hogyoku