Patents by Inventor Mickey H. Yu
Mickey H. Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Structure including polycrystalline resistor with dopant-including polycrystalline region thereunder
Patent number: 11637173Abstract: A structure includes a semiconductor substrate, and a polycrystalline resistor region over the semiconductor substrate. The polycrystalline resistor region includes a semiconductor material in a polycrystalline morphology. A dopant-including polycrystalline region is between the polycrystalline resistor region and the semiconductor substrate.Type: GrantFiled: September 29, 2020Date of Patent: April 25, 2023Assignee: GlobalFoundries U.S. Inc.Inventors: Yves T. Ngu, Siva P. Adusumilli, Steven M. Shank, Michael J. Zierak, Mickey H. Yu -
Patent number: 11444149Abstract: A resistor includes at least one polysilicon resistor element in a semiconductor substrate with each polysilicon resistor element having a continuous U-shape with a continuous lateral bottom. The resistor may include an insulator within a valley of the U-shape of each polysilicon resistor element. A plurality of polysilicon resistor elements can be sequentially interconnected to create a serpentine polysilicon resistor. The resistor may also include a dopant-including high resistivity (HR) polysilicon layer thereunder to provide electrical isolation from, and better thermal conduction to, for example, a base semiconductor substrate. The resistor can be used in an SOI substrate. A related method is also disclosed.Type: GrantFiled: February 23, 2021Date of Patent: September 13, 2022Assignee: GlobalFoundries U.S. Inc.Inventors: Siva P. Adusumilli, Steven M. Shank, Yves T. Ngu, Mickey H. Yu
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Publication number: 20220271116Abstract: A resistor includes at least one polysilicon resistor element in a semiconductor substrate with each polysilicon resistor element having a continuous U-shape with a continuous lateral bottom. The resistor may include an insulator within a valley of the U-shape of each polysilicon resistor element. A plurality of polysilicon resistor elements can be sequentially interconnected to create a serpentine polysilicon resistor. The resistor may also include a dopant-including high resistivity (HR) polysilicon layer thereunder to provide electrical isolation from, and better thermal conduction to, for example, a base semiconductor substrate. The resistor can be used in an SOI substrate. A related method is also disclosed.Type: ApplicationFiled: February 23, 2021Publication date: August 25, 2022Inventors: Siva P. Adusumilli, Steven M. Shank, Yves T. Ngu, Mickey H. Yu
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STRUCTURE INCLUDING POLYCRYSTALLINE RESISTOR WITH DOPANT-INCLUDING POLYCRYSTALLINE REGION THEREUNDER
Publication number: 20220102480Abstract: A structure includes a semiconductor substrate, and a polycrystalline resistor region over the semiconductor substrate. The polycrystalline resistor region includes a semiconductor material in a polycrystalline morphology. A dopant-including polycrystalline region is between the polycrystalline resistor region and the semiconductor substrate.Type: ApplicationFiled: September 29, 2020Publication date: March 31, 2022Inventors: Yves T. Ngu, Siva P. Adusumilli, Steven M. Shank, Michael J. Zierak, Mickey H. Yu -
Publication number: 20200135856Abstract: The disclosure provides an apparatus for preventing an integrated circuit (IC) structure from entering a latch-up mode. In an embodiment, the apparatus may include: a p-type substrate; an n-well within the p-type substrate; an n-type region within the p-type substrate, the n-type region being distinct from the n-well; a p-type region within the n-well; a power supply electrically coupled to the p-type region within the n-well; and a directional diode electrically coupling the power supply to the n-well in parallel with the p-type region. The directional diode biases a current flow from the power supply to the n-well, and the directional diode contacts the n-well distal to the p-type region.Type: ApplicationFiled: October 31, 2018Publication date: April 30, 2020Inventors: Shunhua T. Chang, Ephrem G. Gebreselasie, Mujahid Muhammad, Xiangxiang Lu, Mickey H. Yu
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Patent number: 10636872Abstract: The disclosure provides an apparatus for preventing an integrated circuit (IC) structure from entering a latch-up mode. In an embodiment, the apparatus may include: a p-type substrate; an n-well within the p-type substrate; an n-type region within the p-type substrate, the n-type region being distinct from the n-well; a p-type region within the n-well; a power supply electrically coupled to the p-type region within the n-well; and a directional diode electrically coupling the power supply to the n-well in parallel with the p-type region. The directional diode biases a current flow from the power supply to the n-well, and the directional diode contacts the n-well distal to the p-type region.Type: GrantFiled: October 31, 2018Date of Patent: April 28, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Shunhua T. Chang, Ephrem G. Gebreselasie, Mujahid Muhammad, Xiangxiang Lu, Mickey H. Yu
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Publication number: 20190229207Abstract: Disclosed is an integrated circuit (IC) structure that incorporates a string of vertical devices. Embodiments of the IC structure include a string of two or more vertical diodes. Other embodiments include a vertical diode/silicon-controlled rectifier (SCR) string and, more particularly, a diode-triggered silicon-controlled rectifier (VDTSCR). In any case, each embodiment of the IC structure includes an N-well in a substrate and, within that N-well, a P-doped region and an N-doped region that abuts the P-doped region. The P-doped region can be anode of a vertical diode and can be electrically connected to the N-doped region (e.g., by a local interconnect or by contacts and metal wiring) such that the vertical diode is electrically connected to another vertical device (e.g., another vertical diode or a SCR with vertically-oriented features). Also disclosed is a manufacturing method that can be integrated with methods of manufacturing vertical field effect transistors (VFETs).Type: ApplicationFiled: January 24, 2018Publication date: July 25, 2019Applicant: GLOBALFOUNDRIES INC.Inventors: Tsung-Che Tsai, Alain F. Loiseau, Robert J. Gauthier, JR., Souvick Mitra, You Li, Mickey H. Yu
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Patent number: 10361293Abstract: Disclosed is an integrated circuit (IC) structure that incorporates a string of vertical devices. Embodiments of the IC structure include a string of two or more vertical diodes. Other embodiments include a vertical diode/silicon-controlled rectifier (SCR) string and, more particularly, a diode-triggered silicon-controlled rectifier (VDTSCR). In any case, each embodiment of the IC structure includes an N-well in a substrate and, within that N-well, a P-doped region and an N-doped region that abuts the P-doped region. The P-doped region can be anode of a vertical diode and can be electrically connected to the N-doped region (e.g., by a local interconnect or by contacts and metal wiring) such that the vertical diode is electrically connected to another vertical device (e.g., another vertical diode or a SCR with vertically-oriented features). Also disclosed is a manufacturing method that can be integrated with methods of manufacturing vertical field effect transistors (VFETs).Type: GrantFiled: January 24, 2018Date of Patent: July 23, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Tsung-Che Tsai, Alain F. Loiseau, Robert J. Gauthier, Jr., Souvick Mitra, You Li, Mickey H. Yu
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Patent number: 9818873Abstract: Various embodiments include methods and integrated circuit structures. In some cases, a method of forming an integrated circuit structure can include: forming a doped silicon layer over a substrate; forming a plurality of fin structures from the doped silicon layer; forming a plurality of gate structures over the plurality of fin structures, each of the plurality of gate structures separated from a neighboring gate structure by a first pitch; forming a mask over the plurality of gate structures, exposing at least one of the plurality of gate structures; removing the at least one of the plurality of gate structures, wherein two of the remaining gate structures after the removing are separated by a second pitch larger than the first pitch; and forming an epitaxial region over the substrate between the two of the remaining gate structures.Type: GrantFiled: October 9, 2015Date of Patent: November 14, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Emre Alptekin, Lars W. Liebmann, Injo Ok, Balasubramanian Pranatharthiharan, Ravikumar Ramachandran, Soon-Cheon Seo, Charan V. V. S. Surisetty, Mickey H. Yu
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Publication number: 20170104100Abstract: Various embodiments include methods and integrated circuit structures. In some cases, a method of forming an integrated circuit structure can include: forming a doped silicon layer over a substrate; forming a plurality of fin structures from the doped silicon layer; forming a plurality of gate structures over the plurality of fin structures, each of the plurality of gate structures separated from a neighboring gate structure by a first pitch; forming a mask over the plurality of gate structures, exposing at least one of the plurality of gate structures; removing the at least one of the plurality of gate structures, wherein two of the remaining gate structures after the removing are separated by a second pitch larger than the first pitch; and forming an epitaxial region over the substrate between the two of the remaining gate structures.Type: ApplicationFiled: October 9, 2015Publication date: April 13, 2017Inventors: Emre Alptekin, Lars W. Liebmann, Injo Ok, Balasubramanian Pranatharthiharan, Ravikumar Ramachandran, Soon-Cheon Seo, Charan V.V.S. Surisetty, Mickey H. Yu
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Patent number: 9431399Abstract: A method for forming a semiconductor device comprises forming a first fin and a second fin on a semiconductor substrate, forming a sacrificial gate stack over a channel region of the first fin and the second fin, depositing a layer of spacer material over the first fin and the second fin, depositing a layer of dielectric material over the layer of spacer material, removing a portion of the dielectric material to form a first cavity that exposes a portion of the first fin, epitaxially growing a first semiconductor material on the exposed portion of the first fin to form a source/drain region on the first fin, depositing a protective layer on the source/drain region on the first fin, removing a portion of the dielectric material to form a second cavity that exposes a portion of the second fin, and epitaxially growing a source/drain region on the second fin.Type: GrantFiled: December 15, 2015Date of Patent: August 30, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Emre Alptekin, Balasubramanian Pranatharthiharan, Sivananda Kanakasabapathy, Ravikumar Ramachandran, Mickey H. Yu
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Publication number: 20160111447Abstract: Merged fin structures for finFET devices and methods of manufacture are disclosed. The method of forming the structure includes forming a plurality of fin structures on an insulator layer. The method further includes forming a faceted structure on adjacent fin structures of the plurality of fin structures. The method further includes spanning a gap between the faceted structures on the adjacent fin structures with a semiconductor material.Type: ApplicationFiled: October 15, 2014Publication date: April 21, 2016Inventors: Andres BRYANT, Brian J. GREENE, Jeffrey B. JOHNSON, Mickey H. YU
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Patent number: 9312274Abstract: Merged fin structures for finFET devices and methods of manufacture are disclosed. The method of forming the structure includes forming a plurality of fin structures on an insulator layer. The method further includes forming a faceted structure on adjacent fin structures of the plurality of fin structures. The method further includes spanning a gap between the faceted structures on the adjacent fin structures with a semiconductor material.Type: GrantFiled: October 15, 2014Date of Patent: April 12, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Andres Bryant, Brian J. Greene, Jeffrey B. Johnson, Mickey H. Yu
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Patent number: 8536018Abstract: A low power maskless inter-well deep trench isolation structure and methods of manufacture such structure are provided. A method includes depositing a plurality of layers over a substrate, and forming a layer over the plurality of layers. The method also includes forming well structures in the substrate, and forming sidewall spacers at opposing sides of the layer. The method further includes forming a self-aligned deep trench in the substrate to below the well structures, by removing the sidewall spacers and portions of the substrate aligned with an opening formed by the removal of the sidewall spacers. The method also includes forming a shallow trench in alignment with the deep trench. The method further includes forming shallow trench isolation structures and deep trench isolation structures by filling the shallow trench and the deep trench with insulator material.Type: GrantFiled: May 9, 2012Date of Patent: September 17, 2013Assignees: International Business Machines Corporation, Toshiba America Electronic Components, Inc.Inventors: Brent A. Anderson, Andres Bryant, Josephine B. Chang, Michael A. Guillorn, Ryoji Hasumi, Edward J. Nowak, Mickey H. Yu
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Patent number: 8028924Abstract: A device and method for providing an integrated circuit with a unique identification. The device is usable on an integrated circuit (IC) for generating an identification (ID) identifying the IC and includes a plurality of identification cells each utilizing one of a four wire resistor, thin film resistors, and an inverter pair. A measurement circuit measures a parameter of each cell and is utilized in generating the ID in response thereto.Type: GrantFiled: September 15, 2009Date of Patent: October 4, 2011Assignee: International Business Machines CorporationInventors: Brent A. Anderson, Andres Bryant, Alain Loiseau, Anthony K. Stamper, Mickey H. Yu
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Publication number: 20110062240Abstract: A device and method for providing an integrated circuit with a unique identification. The device is usable on an integrated circuit (IC) for generating an identification (ID) identifying the IC and includes a plurality of identification cells each utilizing one of a four wire resistor, thin film resistors, and an inverter pair. A measurement circuit measures a parameter of each cell and is utilized in generating the ID in response thereto.Type: ApplicationFiled: September 15, 2009Publication date: March 17, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brent A. ANDERSON, Andres BRYANT, Alain LOISEAU, Anthony K. STAMPER, Mickey H. YU
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Patent number: 7723178Abstract: A semiconductor structure fabrication method. The method includes providing a semiconductor structure which includes a first semiconductor layer and a dielectric bottom portion in the first semiconductor layer. A second semiconductor layer on the first semiconductor layer is formed. The first and second semiconductor layers include a semiconductor material. A dielectric top portion and a first STI (Shallow Trench Isolation) region are formed in the second semiconductor layer. The dielectric top portion is in direct physical contact with the dielectric bottom portion.Type: GrantFiled: July 18, 2008Date of Patent: May 25, 2010Assignee: International Business Machines CorporationInventors: James William Adkisson, Andres Bryant, Anthony Kendall Stamper, Mickey H. Yu
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Publication number: 20100015765Abstract: A semiconductor structure fabrication method. The method includes providing a semiconductor structure which includes a first semiconductor layer and a dielectric bottom portion in the first semiconductor layer. A second semiconductor layer on the first semiconductor layer is formed. The first and second semiconductor layers include a semiconductor material. A dielectric top portion and a first STI (Shallow Trench Isolation) region are formed in the second semiconductor layer. The dielectric top portion is in direct physical contact with the dielectric bottom portion.Type: ApplicationFiled: July 18, 2008Publication date: January 21, 2010Inventors: James William Adkisson, Andres Bryant, Anthony Kendall Stamper, Mickey H. Yu
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Publication number: 20090267156Abstract: Device structures and design structures for a static random access memory. The device structure includes a well of a first conductivity type in a semiconductor layer, first and second deep trench isolation regions in the semiconductor layer that laterally bound a device region in the well, and first and second pluralities of doped regions of a second conductivity type in the first device region. A shallow trench isolation region extends laterally across in the device region to connect the first and second deep trench isolation regions, and is disposed in the device region between the first and second pluralities of doped regions. The shallow trench isolation region extends from the top surface into the semiconductor layer to a first depth such that the well is continuous beneath the shallow trench isolation region. A gate stack controls carrier flow between a pair of the first plurality of doped regions.Type: ApplicationFiled: April 29, 2008Publication date: October 29, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brent A. Anderson, Andres Bryant, Josephine B. Chang, Michael A. Guillorn, Ryoji Hasumi, Edward J. Nowak, Mickey H. Yu
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Publication number: 20090269897Abstract: Methods for fabricating dual-depth trench isolation regions for a memory cell. First and second deep trench isolation regions are formed in the semiconductor layer that laterally bound a device region in a well of a first conductivity type in the semiconductor layer. First and second pluralities of doped regions of a second conductivity type are formed in the device region. A shallow trench isolation region is formed that extends laterally across the device region from the first deep trench isolation region to the second deep trench isolation region. The shallow trench isolation region is disposed in the device region between the first and second pluralities of doped regions. The shallow trench isolation region extends into the semiconductor layer to a depth such that the well is continuous beneath the shallow trench isolation region. A gate stack controls carrier flow between a pair of the first plurality of doped regions.Type: ApplicationFiled: April 29, 2008Publication date: October 29, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brent A. Anderson, Andres Bryant, Josephine B. Chang, Michael A. Guillorn, Ryoji Hasumi, Edward J. Nowak, Mickey H. Yu