Method for forming merged contact for semiconductor device
A method for forming a semiconductor device comprises forming a first fin and a second fin on a semiconductor substrate, forming a sacrificial gate stack over a channel region of the first fin and the second fin, depositing a layer of spacer material over the first fin and the second fin, depositing a layer of dielectric material over the layer of spacer material, removing a portion of the dielectric material to form a first cavity that exposes a portion of the first fin, epitaxially growing a first semiconductor material on the exposed portion of the first fin to form a source/drain region on the first fin, depositing a protective layer on the source/drain region on the first fin, removing a portion of the dielectric material to form a second cavity that exposes a portion of the second fin, and epitaxially growing a source/drain region on the second fin.
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The present invention generally relates to semiconductor devices, and more specifically, to contacts for semiconductor devices.
Field effect transistors (FETs) are widely used in the electronics industry for switching, amplification, filtering, and other tasks related to both analog and digital electrical signals. Most common among these are metal-oxide-semiconductor field-effect transistors (MOSFET), in which a gate structure is energized to create an electric field in an underlying channel region of a semiconductor body, by which electrons are allowed to travel through the channel between a source region and a drain region of the semiconductor body. Complementary metal-oxide-semiconductor field-effect transistor, which are typically referred to as CMOS devices, have become widely used in the semiconductor industry. These CMOS devices include both n-type and p-type (NMOS and PMOS) transistors, and therefore promote the fabrication of logic and various other integrated circuitry.
The escalating demands for high density and performance associated with ultra large scale integrated (VLSI) circuit devices have required certain design features, such as shrinking gate lengths, high reliability and increased manufacturing throughput. The continued reduction of design features has challenged the limitations of conventional fabrication techniques. Three-dimensional semiconductor devices, such as fin-type semiconductor devices (referred to as finFETs), typically include dielectric gate spacers formed on sidewalls of the gate stack to isolate the gate stack from the adjacent source/drain (S/D) regions.
The continued demand to scale down the size of finFET devices has required forming semiconductor fins with reduced fin pitches.
Semiconductor devices such as, for example, finFETs have fins formed from semiconductor material to define active regions of the device. The active regions include a channel region and source and drain regions.
The source and drain regions include dopants that may be imbedded in the source and drain regions. The source and drain regions may be formed by an epitaxial growth process that grows a semiconductor material on the fins. The epitaxial growth process may include insitu doping of the source and drain regions.
SUMMARYAccording to an embodiment of the invention, a method for forming a semiconductor device comprises forming a first fin and a second fin on a semiconductor substrate, forming a sacrificial gate stack over a channel region of the first fin and the second fin, depositing a layer of spacer material over the first fin and the second fin, depositing a layer of dielectric material over the layer of spacer material, removing a portion of the dielectric material to form a first cavity that exposes a portion of the first fin, epitaxially growing a first semiconductor material on the exposed portion of the first fin to form a source/drain region on the first fin, depositing a layer of protective material on the source/drain region on the first fin, removing a portion of the dielectric material to form a second cavity that exposes a portion of the second fin, and epitaxially growing a second semiconductor material on the exposed portion of the second fin to form a source/drain region on the second fin.
According to another embodiment of the invention, a method for forming a semiconductor device comprises forming a first fin and a second fin on a semiconductor substrate, forming a sacrificial gate stack over a channel region of the first fin and the second fin, depositing a layer of spacer material over the first fin and the second fin, depositing a layer of dielectric material over the layer of spacer material, removing a portion of the dielectric material to form a first cavity that exposes a portion of the first fin, removing a portion of the first fin to recess the first fin, epitaxially growing a first semiconductor material on the exposed portion of the first fin to form a source/drain region on the first fin, depositing a layer of protective material on the source/drain region on the first fin, removing a portion of the dielectric material to form a second cavity that exposes a portion of the second fin, and epitaxially growing a second semiconductor material on the exposed portion of the second fin to form a source/drain region on the second fin.
According to yet another embodiment of the invention, a semiconductor device comprises a first semiconductor fin arranged on a substrate, a gate stack arranged over a channel region of the first semiconductor fin, a first source/drain region comprising an epitaxially grown semiconductor material on a surface of the first semiconductor fin, a conductive metal material arranged substantially around the first source/drain region, and a dielectric material arranged adjacent to the first semiconductor fin, adjacent to the conductive metal material and over the conductive metal material.
In finFET devices, the reduced scaling of the fin pitch, the gate regions, and active regions may be incompatible with wide source/drain regions and wide contacts. Increasing the length of the contacts reduces parasitic resistance. A reduced contact to gate cross sectional area reduces gate to contact parasitic capacitance.
The embodiments described herein provide for reduces lateral spreading of the epitaxially grown source/drain regions and a reduced gate to contact capacitance.
The following definitions and abbreviations are to be used for the interpretation of the claims and the specification. As used herein, the terms “comprises,” “comprising,” “includes,” “including,” “has,” “having,” “contains” or “containing,” or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a composition, a mixture, process, method, article, or apparatus that comprises a list of elements is not necessarily limited to only those elements but can include other elements not expressly listed or inherent to such composition, mixture, process, method, article, or apparatus.
As used herein, the articles “a” and “an” preceding an element or component are intended to be nonrestrictive regarding the number of instances (i.e. occurrences) of the element or component. Therefore, “a” or “an” should be read to include one or at least one, and the singular word form of the element or component also includes the plural unless the number is obviously meant to be singular.
As used herein, the terms “invention” or “present invention” are non-limiting terms and not intended to refer to any single aspect of the particular invention but encompass all possible aspects as described in the specification and the claims.
As used herein, the term “about” modifying the quantity of an ingredient, component, or reactant of the invention employed refers to variation in the numerical quantity that can occur, for example, through typical measuring and liquid handling procedures used for making concentrates or solutions. Furthermore, variation can occur from inadvertent error in measuring procedures, differences in the manufacture, source, or purity of the ingredients employed to make the compositions or carry out the methods, and the like. In one aspect, the term “about” means within 10% of the reported numerical value. In another aspect, the term “about” means within 5% of the reported numerical value. Yet, in another aspect, the term “about” means within 10, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the reported numerical value.
It will also be understood that when an element, such as a layer, region, or substrate is referred to as being “on” or “over” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or “directly over” another element, there are no intervening elements present, and the element is in contact with another element.
It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.
The fins 104 may be formed in the substrate 102 by depositing a hard mask (not shown) material over the substrate 102. The fins 104 are patterned in NFET 106 and PFET 108 regions by, for example, sidewall imaging transfer or another photolithographic patterning and etching process.
The growth of the source/drain regions 1902 while the source/drain regions 1302 are protected by the protective layer 1502 isolates the growth of the source/drain regions 1902 to the exposed regions of the fins 104b. Thus, the source/drain regions 1302 and 1902 may include different semiconductor materials and/or different types of dopants and dopant concentrations.
The high-k dielectric material layer may be formed by suitable deposition processes, for example, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), evaporation, physical vapor deposition (PVD), chemical solution deposition, or other like processes. The thickness of the high-k dielectric material may vary depending on the deposition process as well as the composition and number of high-k dielectric materials used. The high-k dielectric material layer may have a thickness in a range from about 0.5 to about 20 nm.
The work function metal(s) may be disposed over the high-k dielectric material. The type of work function metal(s) depends on the type of transistor and may differ between the NFET 101 and the PFET 102. Non-limiting examples of suitable work function metals include p-type work function metal materials and n-type work function metal materials. P-type work function materials include compositions such as ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, or any combination thereof. N-type metal materials include compositions such as hafnium, zirconium, titanium, tantalum, aluminum, metal carbides (e.g., hafnium carbide, zirconium carbide, titanium carbide, and aluminum carbide), aluminides, or any combination thereof.
A conductive metal is deposited over the high-k dielectric material(s) and workfunction layer(s) to form the gate stacks. Non-limiting examples of suitable conductive metals include aluminum (Al), platinum (Pt), gold (Au), tungsten (W), titanium (Ti), or any combination thereof. The conductive metal may be deposited by a suitable deposition process, for example, CVD, PECVD, PVD, plating, thermal or e-beam evaporation, and sputtering.
A planarization process, for example, chemical mechanical planarization (CMP), is performed to polish the surface of the conductive gate metal.
Following the formation of the source/drain regions 3302, a protective layer is deposited over the source drain regions 3302 in a similar manner as described above in
Following the formation of the source/drain regions 3502 the process flow may continue in a similar manner as discussed above and shown in
The methods and embodiments described above provide for a finFET device with improved source/drain regions that have a longer length and smaller cross-sectional width that reduces undesirable resistance in the contacts. Further, the reduced height of the contacts adjacent to the gate stacks reduces undesirable parasitic contact to gate capacitance.
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
Claims
1. A method for forming a semiconductor device, the method comprising:
- forming a first fin and a second fin on a semiconductor substrate;
- forming a sacrificial gate stack over a channel region of the first fin and a channel region of the second fin;
- depositing a layer of spacer material over the first fin and the second fin;
- depositing a layer of dielectric material over the layer of spacer material;
- removing a portion of the dielectric material to form a first cavity that exposes a portion of the first fin;
- growing a first semiconductor material on the exposed portion of the first fin to form a source/drain region on the first fin;
- depositing a layer of protective material on the source/drain region on the first fin;
- removing a portion of the dielectric material to form a second cavity that exposes a portion of the second fin; and
- growing a second semiconductor material on the exposed portion of the second fin to form a source/drain region on the second fin.
2. The method of claim 1, further comprising forming a silicide on the source/drain region on the first fin and on the source/drain region of the second fin.
3. The method of claim 1, further comprising depositing a conductive metal in the first cavity and the second cavity.
4. The method of claim 3, further comprising:
- removing a portion of the conductive metal in the first cavity and the second cavity to reduce the height of the conductive metal in the first cavity and the second cavity; and
- depositing a dielectric material over the conductive metal in the first cavity and the second cavity.
5. The method of claim, 1, further comprising removing the layer of protective material to expose the source/drain region on the first fin after epitaxially growing the second semiconductor material.
6. The method of claim 1, wherein the layer of protective material includes a nitride material.
7. The method of claim 1, wherein the removing the portion of the dielectric material to form the first cavity includes removing a portion of the layer of spacer material.
8. The method of claim 1, wherein the first semiconductor material is dissimilar from the second semiconductor material.
9. A method for forming a semiconductor device, the method comprising:
- forming a first fin and a second fin on a semiconductor substrate;
- forming a sacrificial gate stack over a channel region of the first fin and the second fin;
- depositing a layer of spacer material over the first fin and the second fin;
- depositing a layer of dielectric material over the layer of spacer material;
- removing a portion of the dielectric material to form a first cavity that exposes a portion of the first fin;
- removing a portion of the first fin to recess the first fin;
- growing a first semiconductor material on the exposed portion of the first fin to form a source/drain region on the first fin;
- depositing a layer of protective material on the source/drain region on the first fin;
- removing a portion of the dielectric material to form a second cavity that exposes a portion of the second fin; and
- growing a second semiconductor material on the exposed portion of the second fin to form a source/drain region on the second fin.
10. The method of claim 9, further comprising forming a silicide on the source/drain region on the first fin and on the source/drain region of the second fin.
11. The method of claim 9, further comprising depositing a conductive metal in the first cavity and the second cavity.
12. The method of claim 11, further comprising:
- removing a portion of the conductive metal in the first cavity and the second cavity to reduce the height of the conductive metal in the first cavity and the second cavity; and
- depositing a dielectric material over the conductive metal in the first cavity and the second cavity.
13. The method of claim 9, further comprising removing the layer of protective material to expose the source/drain region on the first fin after epitaxially growing the second semiconductor material.
14. The method of claim 9, wherein the layer of protective material includes a nitride material.
15. The method of claim 9, wherein the removing the portion of the dielectric material to form the first cavity includes removing a portion of the layer of spacer material.
16. The method of claim 9, further comprising, removing a portion of the second fin to recess the second fin prior to epitaxially growing the second semiconductor material on the exposed portion of the second fin to form the source/drain region on the second fin.
17. The method of claim 9, wherein the first semiconductor material is dissimilar from the second semiconductor material.
18. A semiconductor device comprising:
- a first semiconductor fin arranged on a substrate;
- a gate stack arranged over a channel region of the first semiconductor fin;
- a first source/drain region comprising an epitaxially grown semiconductor material on a surface of the first semiconductor fin;
- a conductive metal material arranged substantially around the first source/drain region; and
- a dielectric material arranged adjacent to the first semiconductor fin, adjacent to the conductive metal material and over the conductive metal material.
19. The semiconductor device of claim 18, further comprising:
- a second semiconductor fin arranged on the substrate adjacent to the first semiconductor fin;
- the gate stack arranged over a channel region of the second semiconductor fin;
- a second source/drain region comprising an epitaxially grown semiconductor material on a surface of the second semiconductor fin;
- the conductive metal material arranged substantially around the second source/drain region; and
- the dielectric material arranged adjacent to the second semiconductor fin, adjacent to the conductive metal material and over the conductive metal material.
20. The semiconductor device of claim 18, wherein the first source/drain region is arranged in a cavity, the cavity being filled with the conductive metal material and the dielectric material.
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Type: Grant
Filed: Dec 15, 2015
Date of Patent: Aug 30, 2016
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION (Armonk, NY)
Inventors: Emre Alptekin (Fishkill, NY), Balasubramanian Pranatharthiharan (Watervliet, NY), Sivananda Kanakasabapathy (Niskayuna, NY), Ravikumar Ramachandran (Pleasantville, NY), Mickey H. Yu (Essex Junction, VT)
Primary Examiner: Dung Le
Application Number: 14/969,533
International Classification: H01L 21/336 (20060101); H01L 27/092 (20060101); H01L 21/8238 (20060101); H01L 29/66 (20060101);