Abstract: Some embodiments include methods of forming graphene-containing switches. A bottom electrode may be formed over a base, and a first electrically conductive structure may be formed to extend upwardly from the bottom electrode. Dielectric material may be formed along a sidewall of the first electrically conductive structure, while leaving a portion of the bottom electrode exposed. A graphene structure may be formed to be electrically coupled with the exposed portion of the bottom electrode. A second electrically conductive structure may be formed on an opposing side of the graphene structure from the first electrically conductive structure. A top electrode may be formed over the graphene structure and electrically coupled with the second electrically conductive structure. The first and second electrically conductive structures may be configured to provide an electric field across the graphene structure.

Abstract: Memory controllers having a data buffer coupled to receive and hold data from a memory device, and an Error Correction Code (ECC) generator/checker coupled to the data buffer. The ECC generator/checker is configured to generate ECC codes for the data and to compare the generated ECC codes with ECC codes received with the data. The memory controllers are configured to permit different ECC coverage area sizes and/or different ECC code types for different portions of the memory device.

Abstract: Some embodiments include methods for fabricating memory cell constructions. A memory cell may be formed to have a programmable material directly against a material having a different coefficient of expansion than the programmable material. A retaining shell may be formed adjacent the programmable material. The memory cell may be thermally processed to increase a temperature of the memory cell to at least about 300° C., causing thermally-induced stress within the memory cell. The retaining shell may provide a stress which substantially balances the thermally-induced stress. Some embodiments include memory cell constructions. The constructions may include programmable material directly against silicon nitride that has an internal stress of less than or equal to about 200 megapascals. The constructions may also include a retaining shell silicon nitride that has an internal stress of at least about 500 megapascals.

Abstract: A metal oxide semiconductor (MOS) structure having a high dielectric constant gate insulator layer containing gold (Au) nano-particles is presented with methods for forming the layer with high step coverage of underlying topography, high surface smoothness, and uniform thickness. The transistor may form part of a logic device, a memory device, a persistent memory device, a capacitor, as well as other devices and systems. The insulator layer may be formed using atomic layer deposition (ALD) to reduce the overall device thermal exposure. The insulator layer may be formed of a metal oxide, a metal oxycarbide, a semiconductor oxide, or semiconductor oxide oxycarbide, and the gold nano-particles in insulator layer increase the work function of the insulator layer and affect the tunneling current and the threshold voltage of the transistor.

Abstract: An integrated circuit includes circuitry, a first conductor coupled to the circuitry, a conductive pad coupled to the first conductor, and a second conductor coupled to the conductive pad. The second conductor would be floating but for its coupling to the conductive pad. The second conductor may be spaced apart from the first conductor by a distance that is substantially equal to a width of a merged spacer that was formed from a merging of single sidewall spacers over a conductive material from which the first and second conductors were formed.

Abstract: Methods for designing, fabricating, and using attenuated phase shift reticles, or photomasks are disclosed. Methods are also disclosed for subdividing the radiation blocking regions of previously fabricated reticles of previously existing designs. The methods may include forming radiation blocking regions that are subdivided, by cut lines, into discrete, spaced apart sections with dimensions (e.g., surface area, etc.) configured to minimize or eliminate the buildup of electrostatic energy by the radiation blocking regions and/or the discharge of electrostatic energy from the radiation blocking regions and the damage that may be caused by such electrostatic discharge. The methods may include configuring the reticle to prevent radiation from passing through the cut lines between adjacent sections of a subdivided radiation blocking region.

Abstract: Structures and methods are disclosed for the electrical isolation of semiconductor devices. A method of forming a semiconductor device may include providing a second integrated device region on a substrate that is spaced apart from a first integrated device region. An isolation region may be interposed between the first integrated device region and the second integrated device region. The isolation region may include an isolation recess that projects into the substrate to a first predetermined depth, and that may be extended to a second predetermined depth.

Abstract: Die assemblies may include a first die abutting a substrate comprising a recess adjacent to the substrate. An adhesive element may be contained within the recess to attach the first die to the substrate. A height of the adhesive element may not contribute to an overall height of the die assembly. In some embodiments, a second die comprising a non-rectangular cross-sectional shape may be situated on the first die. Die assemblies ma also comprise a first die on a substrate and comprising a cavity on a side of the first die opposing a side on which the support substrate is located. A second die may be at least partially disposed in the cavity. Die assemblies may also comprise a first die secured to a substrate and partially inserted into a recess of a second die on a side opposing a side on which the substrate is located.

Abstract: Horizontally oriented and vertically stacked memory cells are described herein. One or more method embodiments include forming a vertical stack having a first insulator material, a first memory cell material on the first insulator material, a second insulator material on the first memory cell material, a second memory cell material on the second insulator material, and a third insulator material on the second memory cell material, forming an electrode adjacent a first side of the first memory cell material and a first side of the second memory cell material, and forming an electrode adjacent a second side of the first memory cell material and a second side of the second memory cell material.

Abstract: Some embodiments include photonic systems. The systems may include a silicon-containing waveguide configured to direct light along a path, and a detector proximate the silicon-containing waveguide. The detector may comprise a detector material which has a lower region and an upper region, with the lower region having a higher concentration of defects than the upper region. The detector material may comprise germanium in some embodiments. Some embodiments include methods of forming photonic systems.

Abstract: A capacitively coupled plasma reactor comprising a processing chamber, a first electrode, a second electrode and a thermoelectric unit. The processing chamber has an upper portion with a gas inlet and a lower portion, and the upper portion is in fluid communication with the lower portion. The first electrode has a front side and a backside and is positioned at the upper portion of the processing chamber. The second electrode is positioned in the lower portion of the processing chamber and is spaced apart from the front side of the first electrode. The thermoelectric unit is positioned proximate to the backside of the first electrode and is capable of heating and cooling the first electrode.

Abstract: A phase change memory array may include at least one cell used to determine whether the array has been altered by thermal exposure over time. The cell may be the same or different from the other cells. In some embodiments, the cell is only read in response to an event. If, in response to that reading, it is determined that the cell has changed state or resistance, it may deduce whether the change is a result of thermal exposure. Corrective measures may then be taken.

Abstract: Methods and apparatus for forming devices using nanotubes. In one embodiment, an apparatus for depositing nanotubes onto a workpiece comprises a vessel configured to contain a deposition fluid having a plurality of nanotubes including first nanotubes having a first characteristic and second nanotubes having a second characteristic. The apparatus further includes a sorting unit in the vessel configured to selectively isolate or otherwise sort the first nanotubes from the second nanotubes, and a field unit in the vessel configured to attach the first nanotubes to the workpiece. For example, the field unit can attach the first nanotubes to the workpiece such that the first nanotubes are at least generally parallel to each other and in a desired orientation relative to the workpiece.

Abstract: Subject matter disclosed herein relates to a multi-level flash memory and a process flow to form same.

Abstract: A method and apparatus for overflow detection and clamping with parallel operand processing for fixed-point multipliers is disclosed. The disclosure predicts when a multiplication of a number of operands will exceed a pre-determined number of bits based upon the fixed-point format of the operands. The prediction is performed in parallel with the multiplication of the operands. The multiplication need not be completed in full, but only to the extent to determine whether overflow exists. If an overflow detection occurs, clamping is instituted. The parallel operation of the overflow detection and the multiplication provides a faster clamping circuit than would otherwise be available from a serial multiplication followed by a clamping analysis.

Abstract: According to some embodiments, a message generated by a downstream device is received at upstream device. The message may, for example, be received via a peripheral interface and may not require a response. It may then be determined that an error is associated with the message, and an alert message may be sent from the upstream device to the downstream device via the peripheral interface.

Abstract: Methods of operating memory devices and electronic systems having memory devices include initiating a boot mode of operation of the memory device in response to receiving a first command, wherein the first command comprises a pattern of two or more command signals, and terminating the boot mode of operation in response to receiving a second command, wherein the second command comprises a pattern of two or more command signals.

Abstract: Partitioned vias, interconnects, and substrates that include such vias and interconnects are disclosed herein. In one embodiment, a substrate has a non-conductive layer and a partitioned via formed in a portion of the non-conductive layer. The non-conductive layer includes a top side, a bottom side, and a via hole extending between the top and bottom sides and including a sidewall having a first section a second section. The partitioned via includes a first metal interconnect within the via on the first section of the sidewall and a second metal interconnect within the via hole on the second section of the sidewall and electrically isolated from the first metal interconnect. In another embodiment, the first metal interconnect is separated from the second metal interconnect by a gap within the via hole.

Abstract: A contact for memory cells and integrated circuits having a conductive layer supported by the sidewall of a dielectric mesa, memory cells incorporating such a contact, and methods of forming such structures.

Abstract: Memory, modules and methods for using error detection with multi-level memory cells where the number of storage levels of the memory cells is an integer power of a non-binary prime number are provided. Additional circuit and methods are disclosed.