Patents by Inventor Miguel Guerrero

Miguel Guerrero has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8121777
    Abstract: Either vehicle traffic or financial markets data is regularly broadcast in a fixed size packet over a wireless network in a push manner to one or more wireless receiver devices located within a particular service coverage region. A data center stores information specific to the particular region including drive-times strings metadata, drive-times data, drive-times route metadata, traffic incident data and financial markets indicators data. The data center decides upon a particular type of information to be placed into a payload of a next packet to be broadcast and pre-formats this information accordingly without receiving any information from the receiver devices. Data structures are provided which contain data representing the drive-times strings metadata, drive-times data, drive-times route metadata, traffic incident data and financial markets indicators data.
    Type: Grant
    Filed: March 7, 2008
    Date of Patent: February 21, 2012
    Assignee: Microsoft Corporation
    Inventors: Miguel Guerrero, Cosmin Corbea
  • Publication number: 20100332988
    Abstract: A mobile media device user interface is described. In one or more implementations, output of a plurality of audio content is monitored by a mobile media device. Each of the audio content was received via a respective one of a plurality of broadcast channels by the mobile media device. A user interface is displayed on a display device of the mobile media device, the user interface describing each of the plurality of audio content and the respective broadcast channel from which the audio content was received.
    Type: Application
    Filed: June 24, 2009
    Publication date: December 30, 2010
    Applicant: MICROSOFT CORPORATION
    Inventors: Jeffrey C. Fong, D. Graham Stinson, Miguel Guerrero
  • Patent number: 7852412
    Abstract: Circuits, methods, and apparatus for measuring a video signal's noise level. The determination can be made based on pixel values for a single video image frame, for example, by comparing pixel color values, luminance, or other parameter for a first and second group of pixels in the frame. Each group of pixels may be part of a line in the frame, and several such measurements may be made along each line of the frame. These measurements can then be further refined depending on the measure noise level. Once a video noise level is determined, a decision on how to further process the video signal can be made. For example, the picture can be filtered or sharpened. The amount of noise filtering can be made dependent on the amount of noise measured.
    Type: Grant
    Filed: February 27, 2006
    Date of Patent: December 14, 2010
    Assignee: NVIDIA Corporation
    Inventors: Miguel A. Guerrero, Stephen D. Lew, Gerrit A. Slavenburg
  • Publication number: 20100010001
    Abstract: Compounds that activate a sphingosine-1-phosphate receptor of the subtype 1 are provided. Certain compounds selectively activate the receptor subtype 1 in relation to the sphinogosine-4-phosphate receptor subtype 3. Uses and methods of inventive compounds for treatment of malconditions wherein activation, agonism, inhibition or antagonism of the S1P1 is medically indicated are provided.
    Type: Application
    Filed: May 14, 2009
    Publication date: January 14, 2010
    Inventors: Edward Roberts, Hugh Rosen, Steven Brown, Miguel A. Guerrero, Xuemei Peng, Ramulu Poddutoori
  • Publication number: 20090228193
    Abstract: Either vehicle traffic or financial markets data is regularly broadcast in a fixed size packet over a wireless network in a push manner to one or more wireless receiver devices located within a particular service coverage region. A data center stores information specific to the particular region including drive-times strings metadata, drive-times data, drive-times route metadata, traffic incident data and financial markets indicators data. The data center decides upon a particular type of information to be placed into a payload of a next packet to be broadcast and pre-formats this information accordingly without receiving any information from the receiver devices. Data structures are provided which contain data representing the drive-times strings metadata, drive-times data, drive-times route metadata, traffic incident data and financial markets indicators data.
    Type: Application
    Filed: March 7, 2008
    Publication date: September 10, 2009
    Applicant: Microsoft Corporation
    Inventors: Miguel Guerrero, Cosmin Corbea
  • Patent number: 7567566
    Abstract: A method and apparatus to perform aging are described. A method to perform timing comprises receiving an address and retrieving an age zone value associated with the received address. A time is then determined using the retrieved age zone value. The determined time may then be associated with the received address.
    Type: Grant
    Filed: August 29, 2003
    Date of Patent: July 28, 2009
    Assignee: Intel Corporation
    Inventors: Kavitha A. Prasad, Miguel A. Guerrero
  • Patent number: 7516126
    Abstract: A method and apparatus to perform a multi-field matching search. A search unit groups single fields of a multiple-field source into a search target having multiple-field keys (MFKs) whose single fields correspond to the single fields in multiple-field vectors (MFVs) of entries in a data structure. The search unit generates a set of queries based, at least in part, on the MFKs, where each query has a different MFK as a lead MFK. The search unit determines, based, at least in part, on a query, whether the non-wildcard values in the MFVs of an entry match the non-wildcard values in corresponding MFKs of the search target.
    Type: Grant
    Filed: June 30, 2003
    Date of Patent: April 7, 2009
    Assignee: Intel Corporation
    Inventors: Miguel Guerrero, Kinyip Sit, Sreenath Kurupati
  • Patent number: 7467151
    Abstract: A data structure for use in database applications. The data structure includes a key database that is searchable via an index table.
    Type: Grant
    Filed: January 25, 2006
    Date of Patent: December 16, 2008
    Assignee: Intel Corporation
    Inventors: Sreenath Kurupati, Miguel A. Guerrero
  • Patent number: 7349981
    Abstract: A system, an apparatus, and a method for dividing an address into at least two parts and searching for an address from a table that matches at least a significant portion of one of those parts. Where a table address having an exact match to a part of the address is found, additional parts of the address may be matched to one or more table addresses iteratively.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: March 25, 2008
    Assignee: Intel Corporation
    Inventor: Miguel A Guerrero
  • Patent number: 7203889
    Abstract: A memory controller includes a write data module to write user data, parity information, and error correction information in a memory. The memory controller includes a read data module to read the user data and parity information, determine whether there is error in the user data based on the parity information, read the error correction information if there is error as determined based on the parity information.
    Type: Grant
    Filed: April 1, 2004
    Date of Patent: April 10, 2007
    Assignee: Intel Corporation
    Inventors: Alpesh B. Oza, Miguel A. Guerrero, Rohit R. Verma
  • Patent number: 7180894
    Abstract: According to some embodiments, a packet of information may be received, and one of K slots for the packet may be selected based on K*R/2r, R being a vector based on the packet and having r bits. The packet may then be transmitted to a remote device via an output port associated with the selected slot.
    Type: Grant
    Filed: May 29, 2002
    Date of Patent: February 20, 2007
    Assignee: Intel Corporation
    Inventor: Miguel A. Guerrero
  • Patent number: 7152140
    Abstract: According to some embodiments, a parity check is provided for ternary content addressable memory. For example, it may be arranged for a read request to be transmitted to a ternary content addressable memory unit. Data content may then be received from the memory unit in response to the read request, a parity check may be performed on the data content. According to some embodiments, parity information may be masked when the memory unit is queried.
    Type: Grant
    Filed: June 18, 2003
    Date of Patent: December 19, 2006
    Assignee: Intel Corporation
    Inventors: Kin Yip Sit, Kavitha A. Prasad, Miguel Guerrero
  • Patent number: 7107202
    Abstract: A method apparatus for hardware and software co-simulation in ASIC development includes developing hardware and software concurrently and co-simulating the hardware and software therebetween via a network while the hardware and software are being developed. The method and apparatus for hardware and software co-simulation allows the software development and testing of hardware and software to start with the design of hardware so as to reduce an overall system development cycle involving ASICs.
    Type: Grant
    Filed: January 31, 2000
    Date of Patent: September 12, 2006
    Assignee: Intel Corporation
    Inventors: Gopal Hegde, Surendra Rathaur, Miguel Guerrero, Anoop Hegde, Ilango Ganga, Amamath Mutt, Simon Sabato
  • Publication number: 20060190517
    Abstract: A system, apparatus, method and article to perform transposition of a matrix arranged in memory as multiple items per word are described. The apparatus may include a media processing node to process media information. The media processing node may include a memory to store the media information as a matrix of items of media information and a transposing element to transpose the items of media information and to store transposed items of media information in the memory. Other embodiments are described and claimed.
    Type: Application
    Filed: February 2, 2005
    Publication date: August 24, 2006
    Inventor: Miguel Guerrero
  • Publication number: 20060122989
    Abstract: A data structure for use in database applications. The data structure includes a key database that is searchable via an index table.
    Type: Application
    Filed: January 25, 2006
    Publication date: June 8, 2006
    Inventors: Sreenath Kurupati, Miguel Guerrero
  • Patent number: 7058642
    Abstract: Method and data structure for a low memory overhead database and apparatus for implementing the same. Under one embodiment, the data structure includes an index table for storing a plurality of entries, each of the entries corresponding to one of a plurality of hash values, with each entry including a section pointer to identify a memory address of one of a plurality of sections of a key database and including valid bits to indicate a size of the respective section of the key database. The key database is stores a plurality of data entries, with each data entry including a search key having one of the plurality of hash values, and wherein the data entries are grouped into the plurality of sections, with each section storing data entries with search keys having the same hash value.
    Type: Grant
    Filed: March 20, 2002
    Date of Patent: June 6, 2006
    Assignee: Intel Corporation
    Inventors: Sreenath Kurupati, Miguel A. Guerrero
  • Publication number: 20060117114
    Abstract: A method according to one embodiment may include transmitting a plurality of packets through control pipeline circuitry of an integrated circuit of a switch. The control pipeline circuitry may be capable of making a plurality of memory requests to memory of the switch in response to the plurality of packets. The method may further comprise staggering the plurality of memory requests so that each of the plurality of memory requests occurs during a different one of a plurality of time slots. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.
    Type: Application
    Filed: November 29, 2004
    Publication date: June 1, 2006
    Inventors: Rohit Verma, Muraleedhara Navada, Miguel Guerrero, Ashwani Oberai
  • Publication number: 20060013212
    Abstract: Techniques for receiving a packet at a first packet forwarding device in a stack of packet forwarding devices, providing a port aggregation table having a plurality of entries, wherein at least one entry identifies a plurality of ports associated with at least two packet forwarding devices in the stack, and using the packet and the port aggregation table to select a port of a packet forwarding device in the stack for sending the packet to a device external to the stack.
    Type: Application
    Filed: July 13, 2004
    Publication date: January 19, 2006
    Inventors: Hartej Singh, Muraleedhara Navada, Miguel Guerrero
  • Publication number: 20050229089
    Abstract: A memory controller includes a write data module to write user data, parity information, and error correction information in a memory. The memory controller includes a read data module to read the user data and parity information, determine whether there is error in the user data based on the parity information, read the error correction information if there is error as determined based on the parity information.
    Type: Application
    Filed: April 1, 2004
    Publication date: October 13, 2005
    Inventors: Alpesh Oza, Miguel Guerrero, Rohit Verma
  • Publication number: 20050147095
    Abstract: Systems and methods for IP multicast packet burst absorption and multithreaded replication architecture are disclosed. Replications of IP multicast packets are performed in a control plane of a network device. The network device may include a data plane for transmitting data between ingress and egress ports and a control plane including a shared transmit/receive queue infrastructure configured to queue incoming multicast packets to be replicated on a per ingress port basis and to queue transmit packets, and a multicast processing engine in communication with the shared queue infrastructure and including a circular replication buffer to facilitate multithreaded replication of multicast packets on a per egress virtual local area network (VLAN) replication basis. The shared transmit/receive queue infrastructure may dynamically allocate memory between the transmit and receive multicast queues.
    Type: Application
    Filed: December 30, 2003
    Publication date: July 7, 2005
    Applicant: Intel Corporation
    Inventors: Miguel Guerrero, Rahul Saxena, Chien-Hsin Lee, Muralidharan Chilukoor