Abstract: A system, an apparatus, and a method for dividing an address into at least two parts and searching for an address from a table that matches at least a significant portion of one of those parts. Where a table address having an exact match to a part of the address is found, additional parts of the address may be matched to one or more table addresses iteratively.

Abstract: The inventive subject matter provides various apparatus and methods to perform high-speed memory read accesses on dynamic random access memories (“DRAMs”) for read-intensive memory applications. In an embodiment, at least one input/output (“I/O”) channel of a memory controller is coupled to a pair of DRAM chips via a common address/control bus and via two independent data busses. Each DRAM chip may include multiple internal memory banks. In an embodiment, identical data is stored in each of the DRAM banks controlled by a given channel. In another embodiment, data is substantially uniformly distributed in the DRAM banks controlled by a given channel, and read accesses are uniformly distributed to all of such banks. Embodiments may achieve 100% read utilization of the I/O channel by overlapping read accesses from alternate banks from the DRAM pair.

Abstract: A method and apparatus to perform a multi-field matching search. A search unit groups single fields of a multiple-field source into a search target having multiple-field keys (MFKs) whose single fields correspond to the single fields in multiple-field vectors (MFVs) of entries in a data structure. The search unit generates a set of queries based, at least in part, on the MFKs, where each query has a different MFK as a lead MFK. The search unit determines, based, at least in part, on a query, whether the non-wildcard values in the MFVs of an entry match the non-wildcard values in corresponding MFKs of the search target.

Abstract: A method and apparatus to perform aging are described.

Abstract: According to some embodiments, a parity check is provided for ternary content addressable memory.

Abstract: An address look-up device includes a search device and a Discriminant Bits (DB)/Longest Prefix Match (LPM) search device. The search device receives an input key and determines one of at least one memory section of a memory device in which to search for a resultant key having a longest prefix matching the input key. The DB/LPM search device receives the input key and the memory reference, and utilizes a DB pattern and a set of LPM rules to determine and provides a determined key.

Abstract: An address lookup device provides information for a lookup value. A lookup value based on a network address in a received packet is received by a discriminant bits search device. A discriminant bits pattern is used to determine a location in an address lookup table based on the lookup value. The discriminant bits search device determines whether the lookup value is located in the location in the address lookup table. The discriminant bits search device outputs next hop information if the lookup value is located in the location in the address lookup table, and outputs default information if the lookup value is not located in the location in the address lookup table.

Abstract: According to some embodiments, a load balancing engine selects one of K slots for a packet of information based on K*R/2r, R being a vector based on the packet and having r bits.

Abstract: A lookup table is modified by either the insertion or deletion of an address. A lookup table modification device receives an update instruction and determines a selected memory section of the lookup table and an address to which the update instruction relates. The selected memory section is updated. The lookup table modification device determines succeeding non-selected memory sections to which the update instruction does not relate, and modifies contents of one address in each of the succeeding non-selected memory sections. The lookup table modification device changes the logical origin of each of the succeeding non-selected memory sections.

Abstract: A data structure for use in database applications. The data structure includes a key database that is searchable via an index table.

Abstract: Described herein is a method and apparatus for high-speed address learning in sorted address tables.