Abstract: An oscillator and a method of fabricating the oscillator are described. The oscillator includes a resonator with a plurality of transmission lines. An oscillation frequency of the oscillator is independent of at least one dimension of the plurality of transmission lines. The oscillator also includes a negative resistance circuit coupled to the resonator that cancels internal loss resistance of the resonator.

Abstract: An oscillator and a method of fabricating the oscillator are described. The oscillator includes a resonator with a plurality of transmission lines. An oscillation frequency of the oscillator is independent of at least one dimension of the plurality of transmission lines. The oscillator also includes a negative resistance circuit coupled to the resonator that cancels internal loss resistance of the resonator.

Abstract: There is provided an integrated electronic circuit. The integrated electronic circuit includes a voltage controlled oscillator and a frequency doubler connected to the voltage controlled oscillator. A frequency doubling input of the frequency doubler is load isolated from an output of the voltage controlled oscillator.

Abstract: There is provided an integrated electronic circuit. The integrated electronic circuit includes a voltage controlled oscillator and a frequency doubler connected to the voltage controlled oscillator. A frequency doubling input of the frequency doubler is load isolated from an output of the voltage controlled oscillator.

Abstract: Systems and method for near-field millimeter wave imaging are provided, in particular, near-field millimeter wave imaging systems and methods that enable sub-wavelength resolution imaging by scanning objects with sub-wavelength probe elements and capturing and measuring phase and intensity of reflected energy to generate images.

Abstract: A polarimetric transceiver front-end includes two receive paths configured to receive signals from an antenna, each receive path corresponding to a respective polarization. Each front-end includes a variable amplifier and a variable phase shifter; a first transmit path configured to send signals to the antenna, where the transmit path is connected to the variable phase shifter of one of the two receive paths and includes a variable amplifier; and a transmit/receive switch configured to select between the first transmit path and the two receive paths for signals, where the transmit/receive switch includes a quarter-wavelength transmission line that adds a high impedance to the transmit path when the transmit/receive switch is in a receiving state.

Abstract: A device and method for measuring jitter includes a capacitive element capable of being selectively charged, wherein the selection is made by a received signal from which an accumulated jitter value is to be determined. An analog-to-digital converter is coupled to the capacitive element to determine a voltage across the capacitive element after a number of cycles of the received signal. A determination module is coupled to the analog-to-digital converter to output the accumulated jitter value of the received signal using the voltage, wherein the accumulated jitter value is accumulated over the number of cycles.

Abstract: A multi-stage amplifier is provided that uses tunable transmission lines, as well as a calibration method for the multi-stage amplifiers. A multi-stage amplifier, comprises a plurality of tunable amplification stages, wherein each of the tunable amplification stages comprises a tunable resonator based on a transmission line having a tunable element. The tunable elements may vary a capacitance or an inductance to tune a frequency of an applied signal. A calibration method is provided for a multi-stage amplifier having a plurality of transmission lines, an input stage and an output stage. The multi-stage amplifier is calibrated by generating a signal to determine a frequency for a substantially maximum power; generating an error signal by comparing the frequency for the substantially maximum power with a desired frequency; varying a digital control code applied to each of the tunable transmission lines, input stage and output stage until the error signal satisfies predefined criteria.

Abstract: Systems and method for near-field millimeter wave imaging are provided, in particular, near-field millimeter wave imaging systems and methods that enable sub-wavelength resolution imaging by scanning objects with sub-wavelength probe elements and capturing and measuring phase and intensity of reflected energy to generate images.

Abstract: Systems and method for near-field millimeter wave imaging are provided, in particular, near-field millimeter wave imaging systems and methods that enable sub-wavelength resolution imaging by scanning objects with sub-wavelength probe elements and capturing and measuring phase and intensity of reflected energy to generate images.

Abstract: An exemplary filter includes N (?2) unity gain amplifiers, each with a pair of differential input terminals and a pair of differential output terminals; a pair of filter differential input terminals; a first pair of variable resistances coupling the pair of filter differential input terminals to the pair of differential input terminals of the first unity gain amplifier; N?1 pairs of variable resistances coupling the pairs of differential output terminals of each of the N unity gain amplifiers, other than the last one, to the pairs of differential input terminals of its downstream neighbor; N?1 pairs of variable capacitances coupling the pairs of differential input terminals of each of the N unity gain amplifiers, other than the last one, to the pairs of differential output terminals of its downstream neighbor; and a variable capacitance coupling the pair of differential input terminals of the last unity gain amplifier to each other.

Abstract: An exemplary filter includes N (?2) unity gain amplifiers, each with a pair of differential input terminals and a pair of differential output terminals; a pair of filter differential input terminals; a first pair of variable resistances coupling the pair of filter differential input terminals to the pair of differential input terminals of the first unity gain amplifier; N?1 pairs of variable resistances coupling the pairs of differential output terminals of each of the N unity gain amplifiers, other than the last one, to the pairs of differential input terminals of its downstream neighbor; N?1 pairs of variable capacitances coupling the pairs of differential input terminals of each of the N unity gain amplifiers, other than the last one, to the pairs of differential output terminals of its downstream neighbor; and a variable capacitance coupling the pair of differential input terminals of the last unity gain amplifier to each other.

Abstract: It is disclosed a combinatorial logic circuit comprising a first logic block (B1) coupled to a supply terminal (VDD) via a first resistor means (RI) and via a second resistor means (R2) for receiving respective first and second supply currents (111, 112). The circuit further comprises a second logic block (B2) coupled to the supply terminal (VDD) via the first resistor means (R1) and via the second resistor means (R2) for receiving respective third and fourth supply currents (122, 121). A first output terminal (Q?) coupled to the first block (B1) and to the first resistor means (R1). A second output terminal (Q+) coupled to the second logic block (B2) and to the second resistor means (R2). A first current source (I0) coupled to at least one of the first output terminal (Q?) and/or second output terminal (Q+) for providing a first supply current (I1) through the first resistor means (R1), which is substantially equal to a second supply current (I2) through the second resistor means (R2).

Abstract: A frequency divider comprising a first flip-flop (M1, M2, M3, M4) having a first clock input (CI) for receiving a clock signal, the flip-flop further comprising a first set input (Q4) and a first non-inverted output (Q1). The frequency divider further comprises a second flip-flop (M?, M?, M?, M?) having a second clock input (CI) for receiving a second clock signal that is substantially in anti-phase with the clock signal inputted into the first clock input (CI), a second set input coupled to the first non-inverted output (Q1), a second non-inverted output (Q2) and a second inverted output (Q2), the second inverted output (Q2) being coupled to the first set input (Q4).

Abstract: The present invention concerns a phase Detector for detecting a phase difference between a data clock DATA-CLK and a reference clock REF-CLK using a data signal DATA. A transition of the data signal DATA is synchronous with a transition of the data clock DATA-CLK. The data clock DATA-CLK and the reference clock REF-CLK have the same frequency. The phase detector comprises a first signal generator (42) for generating a first binary signal ERRQ, a pulse width of which is equal to a first time difference ?T1 between a transition of the data signal DATA and a transition of a first reference clock signal CKQ adjacent to the transition of the data signal DATA, wherein the first signal generator comprises an input for receiving the first reference clock signal CKQ and an input for receiving the data signal DATA. The phase detector comprises a second signal generator (40) for generating a second binary signal ERRI.

Abstract: Linear phase detectors comprising circuits (1,2) receiving reference signals (REF) and first and second clock signals (CLK-Q, CLK-I) for generating first and second (phase) control signals (UP,DOWN) for use in multiplier circuits, demodulators and receivers, have large delays due to long path lengths and many operations between input and output (insight). They can be made faster by providing each circuit (1,2) with two parallel latches (10,11,20,21) and a multiplexer (12,22) for multiplexing latch output signals (basic idea). Said multiplexers generate (frequency control) signals to be supplied to frequency detectors, with a third circuit (3) generating at least one of said (phase) control signals (UP,DOWN). Said third circuit (3) comprises a latch (30) generating said first (phase) control signal (UP), with one of the latches (20) of the second circuit (2) generating the second (phase) control signal (DOWN. Or said third circuit (3) comprises logical circuitry (31-34) comprising four EXOR gates (31-34).

Abstract: A linear amplifier circuit comprising a first differential amplifier (DA 1) having a differential input terminals (I+, I?) for receiving a binary input signal, and a differential output terminals (O+,O?), a second differential amplifier (DA2) having input terminals coupled to the differential input terminals (I+, I?). The amplifier further comprises, a third differential amplifier (DA3) coupled in cascade to the second differential amplifier (DA2) and having its output cross-coupled to the differential output terminals in a feedforward connection, and a capacitor (C) coupled to the third differential amplifier (DA3) for determining an increase of a bandwidth of the linear amplifier, a current flowing through the capacitor (C) being proportional with a derivative of the differential input signal (I+, I?).

Abstract: Charge pump for providing an output current for charging and discharging a filter in accordance with an input signal, said charge pump comprising a first current source connectable with the input signal for driving the current source and adapted to providing a first current equal to a constant current Io plus a variable current ?x, said variable current ?x being directly proportional to the input signal, a second current source connectable with the input signal for driving the current source and adapted to providing a second current equal to the constant current I0 minus said variable current ?x, and an output for providing the output current, wherein said output is connected to both the first and second current source in such a way, that the output current is equal to a difference between the first and second current.

Abstract: A tracking data cell (10) comprising: —a pair of track and hold circuits (1, 1?) coupled to a first multiplexer (5), —a clock signal (H+, H?) being inputted substantially in anti-phase in the respective track and hold circuits (1, 1?) for determining a receipt of a data signal (D+, D?) having a rate, —said track and hold circuits (1, 1?) providing an output signal (O) having a substantially half rate.

Abstract: A track and hold circuit (1) comprising: —a linear amplifier (2) receiving a differential analog signal (D+, D?) and being controlled by a first binary clock signal (H+) having a first phase, —the linear amplifier (2) providing a feed-forward input signal substantially equal with the differential analog signal (D+, D?) to a pseudo latch circuit (3) in the first phase of the first binary clock signal (H+), said pseudo latch circuit (3) being controlled by a second binary clock signal (H?) for memorizing the input signal and providing a differential output signal (LD+, LD?) substantially equal with the input signal during a second phase of the first binary clock signal (H?), the second binary clock signal being substantially in antiphase with the first binary clock signal (H+).