Abstract: Linear phase detectors comprising circuits (1,2) receiving first and second clock signals (CLKOO, CLK90) for generating first and second control signals (UP,DOWN) for use in clock extractors and data regenerators have large delays due to long path lengths and many operations between input and output (insight). They can be made faster by providing each circuit (1,2) with two parallel latches (10,11,20,21) and a multiplexer (12,22) for multiplexing latch output signals (basic idea). A data signal is supplied to the first circuit (1), and a first circuit output signal is supplied to the second circuit (2). By introducing a third and a fourth circuit (3,4) each also comprising two latches and a multiplexer, a fast linear phase detector has been constructed having a gain which is independent from the number of transitions in the data signal, which is advantageous. Logical circuitry (13,23) of each circuit (1,2,3,4) is coupled to an adder/subtracter (5).

Abstract: Known phase detectors have feedbackloops and do not function properly under severe conditions. By providing said phase detectors with difference establishers (1) for establishing differences between input signals and with selectors (2) for selecting one of said differences to be used as an output signal for phase locking purposes, the phase detectors operate better under more severe conditions, with any dead-zone having disappeared. Said selector (2) is a feedbackless selector, then a loop delay no longer exists, the linear range will not get any smaller for higher frequencies, the output jitter will not increase, for sampled input signals. Said selector (2) comprises latches (21,22) and a multiplexer (23). A converter (3) converts input signals into compensated input signals, via a buffer circuit (31,33) coupled to a replica circuit (32,34) per input signal, to provide input signals having substantially equal amplitudes and being compensated with process errors and temperature variations.

Abstract: A Phase Locked Loop (1) used in a data and clock recovery comprising a frequency detector (10) including a quadricorrelator (2), the quadricorrelator (2) comprising a frequency detector including double edge clocked bi-stable circuits (21, 22, 23, 24) coupled to a first multiplexer (31) and to a second multiplexer (32) being controlled by a signal having a same bitrate as the incoming signal (D), and a phase detector (DFF) controlled by a first signal pair (PQ, {overscore (PQ)} provided by the first multiplexer (31) and by a second signal pair (PI, {overscore (PI)}) provided by the second multiplexer (32).

Abstract: A Phase Locked Loop (1) comprising a frequency detector (10) including a balanced quadricorrelator (2), the loop (1) being characterized in that the quadricorrelator (2) comprises double edge clocked bi-stable circuits (21, 22, 23, 24, 25, 26, 27, 28) coupled to multiplexers (31, 32, 33, 34) being controlled by a signal having the same bitrate as the incoming D signal (D).

Abstract: Voltage controlled oscillator comprising a LC tank circuit (L, C, R) coupled to modulator means (2) and characterized in that the modulator means (2) are coupled to amplifier means (1) via an adder (3) for generating a quadrature periodical output signal having a frequency in a relative wide range, the frequency being controlled by a control signal (VT) provided to the modulator means (2).