Abstract: A driver circuit includes digital inputs, such as a first digital input and a second digital input. The digital inputs receive voltages at either a digital high-voltage or a digital low-voltage. The driver circuit has a clock input, an analog output, a first differential pair of transistors connected to the analog output, second differential pairs of transistors connected to the analog output, and voltage limiters connected to the clock input and the second differential pairs of transistors. The voltage limiters supply different voltages to the second differential pairs of transistors, which results in the second differential pairs of transistors providing analog signals to the analog output that are at different voltage steps at, and between, the digital high-voltage and the digital low-voltage.

Abstract: A driver circuit includes digital inputs, such as a first digital input and a second digital input. The digital inputs receive voltages at either a digital high-voltage or a digital low-voltage. The driver circuit has a clock input, an analog output, a first differential pair of transistors connected to the analog output, second differential pairs of transistors connected to the analog output, and voltage limiters connected to the clock input and the second differential pairs of transistors. The voltage limiters supply different voltages to the second differential pairs of transistors, which results in the second differential pairs of transistors providing analog signals to the analog output that are at different voltage steps at, and between, the digital high-voltage and the digital low-voltage.

Abstract: An oscillator includes N greater than unity gain amplifiers, N being at least two. Each of the N greater than unity gain amplifiers has a pair of differential input terminals and a pair of differential output terminals. The oscillator further includes a first pair of variable resistances, N?1 pairs of variable resistances, N?1 pairs of variable capacitances, and a variable capacitance. The pairs of variable resistances couple differential output terminals of the N greater than unity gain amplifiers. The pairs of variable capacitances couple differential input terminals of the N greater than unity gain amplifiers. Each of the N greater than unity gain amplifiers includes a linearized operational transconductance amplifier stage coupled to a corresponding pair of the differential input terminals, and a unity gain buffer with feedback interconnected between the linearized operational transconductance amplifier stage and a corresponding pair of the differential output terminals.

Abstract: An exemplary differential track and hold amplifier includes a track stage including first and second linearized pairs connected in series at their respective inputs and in parallel at their respective outputs. The differential track and hold amplifier also includes a hold stage selectively coupled to the outputs of the first and second linearized pairs. The hold stage includes a unity gain buffer with feedback having a hold capacitor interconnected across its outputs. The differential track and hold amplifier also includes an output buffer coupled to the outputs of the hold stage. An exemplary analog-to-digital converter includes a differential track-and-hold amplifier, a voltage ladder, and a plurality of slices.

Abstract: An exemplary differential track and hold amplifier includes a track stage including first and second linearized pairs connected in series at their respective inputs and in parallel at their respective outputs. The differential track and hold amplifier also includes a hold stage selectively coupled to the outputs of the first and second linearized pairs. The hold stage includes a unity gain buffer with feedback having a hold capacitor interconnected across its outputs. The differential track and hold amplifier also includes an output buffer coupled to the outputs of the hold stage. An exemplary analog-to-digital converter includes a differential track-and-hold amplifier, a voltage ladder, and a plurality of slices.

Abstract: A detector arrangement for detecting a frequency error between an input signal (DATA) and a reference signal. The detector arrangement comprising first latch circuitry (L1, L2) for sampling a quadrature component (CKQ) of the reference signal based on the input signal, to generate a first binary signal (PDQ); second latch circuitry (L3, L4) for sampling an in-phase component (CKI) of the reference signal based on the input signal, to-generate a second binary signal (PD I); third latch circuitry (L5) for sampling the first binary signal based on the second binary signal, to generate the frequency error signal (FD). The detector further comprising control circuitry (TS) for selectively suppressing operation of a charge pump (82) to which the first binary signal (PDQ) is supplied, in response to a control signal derived from the second binary signal.

Abstract: Charge pump for providing an output current for charging and discharging a filter in accordance with an input signal, said charge pump comprising a first current source connectable with the input signal for driving the current source and adapted to providing a first current equal to a constant current Io plus a variable current ?x, said variable current ?x being directly proportional to the input signal, a second current source connectable with the input signal for driving the current source and adapted to providing a second current equal to the constant current Io minus said variable current ?x, and an output for providing the output current, wherein said output is connected to both the first and second current source in such a way, that the output current is equal to a difference between the first and second current.

Abstract: A node detection system includes an array of nodes (510), wherein each node of the array of nodes (510) has at least at least two, three or four directional antennas (530) configured to have antenna beams in as many directions. The range of each antenna is limited to reach a neighboring operational node of the array of nodes (510) for transmission of a message to the neighboring operational node. A controller (550) is configured to receive messages from the array of nodes (510) and determine the location of each node based on the messages.

Abstract: It is disclosed a combinatorial logic circuit comprising a first logic block (B1) coupled to a supply terminal (VDD) via a first resistor means (RI) and via a second resistor means (R2) for receiving respective first and second supply currents (111, 112). The circuit further comprises a second logic block (B2) coupled to the supply terminal (VDD) via the first resistor means (R1) and via the second resistor means (R2) for receiving respective third and fourth supply currents (122, 121). A first output terminal (Q?) coupled to the first block (B1) and to the first resistor means (R1). A second output terminal (Q+) coupled to the second logic block (B2) and to the second resistor means (R2). A first current source (I0) coupled to at least one of the first output terminal (Q?) and/or second output terminal (Q+) for providing a first supply current (I1) through the first resistor means (R1), which is substantially equal to a second supply current (I2) through the second resistor means (R2).

Abstract: Devices (1,2) comprising feedback-less amplifiers (16,19,26,29) that are gain controlled introduce linear relationships between output signals and input signals of the feedback-less amplifiers (16,19,26,29) by providing the feedback-less amplifiers (16,19,26,29) sub-circuits in the form of first transistors (33) operated in their triode regions for receiving input signals and second sub-circuits in the form of second transistors (34) for receiving control signals and third sub-circuits in the form of resistors (35) for generating output signals, whereby the respective first and second and third sub-circuits form a serial path. Second circuits (4) receive gain signals and convert the gain signals into the control signals. The control signals are copies of the gain signals. The second circuits (4) comprise current sources (6) and third and fourth transistors (41,42). The current sources (6) comprise fifth and sixth transistors (61,62).

Abstract: A Phase Locked Loop (1) used in a data and clock recovery comprising a frequency detector (10) including a quadricorrelator (2), the quadricorrelator (2) comprising a frequency detector including double edge clocked bi-stable circuits (21, 22, 23, 24) coupled to a first multiplexer (31) and to a second multiplexer (32) being controlled by a signal having a same bitrate as the incoming signal (D), and a phase detector (DFF) controlled by a first signal pair (PQ, PQ provided by the first multiplexer (31) and by a second signal pair (PI, PI) provided by the second multiplexer (32).

Abstract: The present invention relates to a detector arrangement and a charge pump circuit for a recovery circuit recovering timing information for random data. The detector arrangement comprises first latch means for sampling a quadrature component of a reference signal based on an input signal, to generate a first binary signal, a second latch means for sampling an in-phase component of the reference signal based on the input signal, to generate a second binary signal, and a third latch means for sampling the first binary signal based on the second binary signal, to generate a frequency error signal. Thus, a simple and fast detection circuitry can be achieved based on a digital implementation. Furthermore, the charge pump circuit comprises a differential input circuit and control means for controlling a tail current of the differential input circuit in response to a frequency-locked state of frequency detector arrangement.

Abstract: The present invention provides a driving circuit (100) in particular for driving a laser diode (700) or a modulator, at data speed in the order of Gb/s. The driving circuit (10) has a low-voltage, high-speed output stage capable of driving efficiently a laser diode (700) or a modulator The driver circuit (10) comprises a chain of circuits, said chain comprising a slew-rate control circuit, at least one translinear amplifier (200, 201, 202), a push/pull stage (300), and an output stage (400) for driving the load current. Due to its versatility, the driver can be used in other applications e.g. line drivers, cable drivers, high-speed serial interfaces for back-plane interconnect, etc. The driver can work at low supply voltages, e.g. 3.3V nominal down to 2.7V, with high power efficiency. One major clue is to use entirely the large signal current produced by the output stage, e.g. in the driven laser diode, without wasting current in supply lines.

Abstract: The present invention relates to a detector arrangement and a charge pump circuit for a recovery circuit recovering timing information for random data. The detector arrangement comprises a first latch circuit for sampling a quadrature component of a reference signal based on an input signal, to generate a first binary signal, a second latch circuit for sampling an in-phase component of the reference signal based on the input signal, to generate a second binary signal, and a third latch circuit for sampling the first binary signal based on the second binary signal, to generate a frequency error signal. Furthermore, the charge pump circuit comprises a differential input circuit and a control circuit for controlling a tail current of the differential input circuit in response to a frequency-locked state of frequency detector arrangement.

Abstract: The present invention relates to an all n-type transistor current mirror for mirroring an input current to an output current. The current mirror comprises an input n-type transistor (T4, QO, T1) interposed between a positive supply plane (VCC) and an input node (104, 202, 310) with its collector being connected to the positive supply plane (VCC) and its emitter being connected to the input node (104, 202, 310). An output n-type transistor (T3, Q1, T2) is interposed between the positive supply plane (VCC) and an output node (106, 204, 314) with its collector being connected to the positive supply plane (VCC) and its emitter being connected to the output node (106, 204, 314). A feedback circuit equals base-emitter voltages of the input (T4, QO, T1) and the output transistor (T3, Q1, T2) in order to mirror the emitter current of the input transistor (T4, QO, T1) to the emitter current of the output transistor (T3, Q1, T2).

Abstract: The present invention provides a driving circuit (100) in particular for driving a laser diode (700) or a modulator, at data speed in the order of Gb/s. The driving circuit (10) has a low-voltage, high-speed output stage capable of driving efficiently a laser diode (700) or a modulator The driver circuit (10) comprises a chain of circuits, said chain comprising a slew-rate control circuit, at least one translinear amplifier (200, 201, 202), a push/pull stage (300), and an output stage (400) for driving the load current. Due to its versatility, the driver can be used in other applications e.g. line drivers, cable drivers, high-speed serial interfaces for back-plane interconnect, etc. The driver can work at low supply voltages, e.g. 3.3V nominal down to 2.7V, with high power efficiency. One major clue is to use entirely the large signal current produced by the output stage, e.g. in the driven laser diode, without wasting current in supply lines.

Abstract: Devices (1,2) comprising feedback-less amplifiers (16,19,26,29) that are gain controlled introduce linear relationships between output signals and input signals of the feedback—less amplifiers (16,19,26,29) by providing the feedback—less amplifiers (16,19,26,29) sub-circuits in the form of first transistors (33) operated in their triode regions for receiving input signals and second sub-circuits in the form of second transistors (34) for receiving control signals and third sub-circuits in the form of resistors (35) for generating output signals, whereby the respective first and second and third sub-circuits form a serial path. Second circuits (4) receive gain signals and convert the gain signals into the control signals. The control signals are copies of the gain signals. The second circuits (4) comprise current sources (6) and third and fourth transistors (41,42). The current sources (6) comprise fifth and sixth transistors (61,62).

Abstract: A latch circuit comprising, a differential input with a non-inverting input (D+) and an inverting input (D?). The latch further comprises a differential output with a non-inverting output (Q+) and an inverting output (Q?). One of the outputs (Q?) is coupled to one of the inputs input (D+) having an opposite polarity. The latch further comprises a control input for receiving a control signal (VcM) for determining a threshold for an input signal (In) such that if the input signal is at larger than the threshold the non-inverting output is in a HIGH logic state and in a LOW state if the input signal is smaller than the threshold.

Abstract: A Phase Locked Loop (1) comprising a frequency detector (10) including a balanced quadricorrelator (2), the loop (1) being characterized in that the quadricorrelator (2) comprises double edge clocked bi-stable circuits (21, 22, 23, 24, 25, 26, 27, 28) coupled to multiplexers (31, 32, 33, 34) being controlled by a signal having the same bitrate as the incoming D signal (D).

Abstract: Known phase detectors have feedbackloops and do not function properly under severe conditions. By providing said phase detectors with difference establishers (1) for establishing differences between input signals and with selectors (2) for selecting one of said differences to be used as an output signal for phase locking purposes, the phase detectors operate better under more severe conditions, with any dead-zone having disappeared. Said selector (2) is a feedbackless selector, then a loop delay no longer exists, the linear range will not get any smaller for higher frequencies, the output jitter will not increase, for sampled input signals. Said selector (2) comprises latches (21,22) and a multiplexer (23). A converter (3) converts input signals into compensated input signals, via a buffer circuit (31,33) coupled to a replica circuit (32,34) per input signal, to provide input signals having substantially equal amplitudes and being compensated with process errors and temperature variations.