Patents by Inventor Mika Tuomi

Mika Tuomi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210398325
    Abstract: Methods, devices, and systems for compressing and decompressing a stream of indices associated with graphics primitives. A group of delta values is determined based on a group of indices of the stream of indices. The group of delta values is compared to delta values in a lookup table. The group of indices is compressed based on an entry in the lookup table if the group of delta values matches all delta values in the entry, otherwise, the group of indices is compressed based on variable-length encoding.
    Type: Application
    Filed: February 26, 2021
    Publication date: December 23, 2021
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Kiia Kallio, Mika Tuomi, Ruijin Wu, Anirudh R. Acharya
  • Publication number: 20210287418
    Abstract: A processor dynamically selects a render mode for each render pass of a frame based on the characteristics of the render pass. A software driver of the processor receives graphics operations from an application executing at the processor and converts the graphics operations into a command stream that is provided to the graphics pipeline. As the driver converts the graphics operations into the command stream, the driver analyzes each render pass of the frame to determine characteristics of the render passes, and selects a render mode for each render pass based on the characteristics of the render pass.
    Type: Application
    Filed: August 31, 2020
    Publication date: September 16, 2021
    Inventors: Anirudh R. ACHARYA, Ruijin WU, Young In YEO, Mika TUOMI, Kiia KALLIO
  • Publication number: 20210225060
    Abstract: A processing device and a method of tiled rendering of an image for display is provided. The processing device includes memory and a processor. The processor is configured to receive the image comprising one or more three dimensional (3D) objects, divide the image into tiles, execute coarse level tiling for the tiles of the image and execute fine level tiling for the tiles of the image. The processing device also includes same fixed function hardware used to execute the coarse level tiling and the fine level tiling. The processor is also configured to determine visibility information for a first one of the tiles. The visibility information is divided into draw call visibility information and triangle visibility information for each remaining tile of the image.
    Type: Application
    Filed: September 25, 2020
    Publication date: July 22, 2021
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Mika Tuomi, Kiia Kallio, Ruijin Wu, Anirudh R. Acharya, Vineet Goel
  • Publication number: 20210209831
    Abstract: A method, system, and non-transitory computer readable storage medium for rasterizing primitives are disclosed. The method, system, and non-transitory computer readable storage medium includes: generating a primitive batch from a sequence of one or more primitives, wherein the primitive batch includes primitives sorted into one or more row groups based on which row of a plurality of rows each primitive intersects; and processing each row group, the processing for each row group including: identifying one or more primitive column intercepts for each of the one or more primitives in the row group, wherein each combination of primitive column intercept and row identifies a bin; and rasterizing the one or more primitives that intersect the bin.
    Type: Application
    Filed: March 22, 2021
    Publication date: July 8, 2021
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Michael Mantor, Laurent Lefebvre, Mikko Alho, Mika Tuomi, Kiia Kallio
  • Publication number: 20210150797
    Abstract: Systems, apparatuses, and methods for implementing light volume rendering techniques are disclosed. A processor is coupled to a memory. A processor renders the geometry of a scene into a geometry buffer. For a given light source in the scene, the processor initiates two shader pipeline passes to determine which pixels in the geometry buffer to light. On the first pass, the processor renders a front-side of a light volume corresponding to the light source. Any pixels of the geometry buffer which are in front of the front-side of the light volume are marked as pixels to be discarded. Then, during the second pass, only those pixels which were not marked to be discarded are sent to the pixel shader. This approach helps to reduce the overhead involved in applying a lighting effect to the scene by reducing the amount of work performed by the pixel shader.
    Type: Application
    Filed: August 31, 2020
    Publication date: May 20, 2021
    Inventors: Mika Tuomi, Miikka Petteri Kangasluoma, Jan Henrik Achrenius, Laurent Lefebvre
  • Patent number: 10957094
    Abstract: A system, method and a computer program product are provided for hybrid rendering with deferred primitive batch binning A primitive batch is generated from a sequence of primitives. Initial bin intercepts are identified for primitives in the primitive batch. A bin for processing is identified. The bin corresponds to a region of a screen space. Pixels of the primitives intercepting the identified bin are processed. Next bin intercepts are identified while the primitives intercepting the identified bin are processed.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: March 23, 2021
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Michael Mantor, Laurent Lefebvre, Mikko Alho, Mika Tuomi, Kiia Kallio
  • Patent number: 10943389
    Abstract: Techniques for removing or identifying overlapping fragments in a fragment stream after z-culling are disclosed. The techniques include maintaining a first-in-first-out buffer that stores post-z-cull fragments. Each time a new fragment is received at the buffer, the screen position of the fragment is checked against all other fragments in the buffer. If the screen position of the fragment matches the screen position of a fragment in the buffer, then the fragment in the buffer is removed or marked as overlapping. If the screen position of the fragment does not match the screen position of any fragment in the buffer, then no modification is performed to fragments already in the buffer. In either case, he fragment is added to the buffer. The contents of the buffer are transmitted to the pixel shader for pixel shading at a later time.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: March 9, 2021
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Laurent Lefebvre, Michael Mantor, Mark Fowler, Mikko Alho, Mika Tuomi, Kiia Kallio, Patrick Klas Rudolf Buss, Jari Antero Komppa, Kaj Tuomi, Christopher J. Brennan
  • Patent number: 10546365
    Abstract: An apparatus, such as a head mounted device (HMD), includes one or more processors configured to implement a graphics pipeline that renders pixels in window space with a nonuniform pixel spacing. The apparatus also includes a first distortion function that maps the non-uniformly spaced pixels in window space to uniformly spaced pixels in raster space. The apparatus further includes a scan converter configured to sample the pixels in window space through the first distortion function. The scan converter is configured to render display pixels used to generate an image for display to a user based on the uniformly spaced pixels in raster space. In some cases, the pixels in the window space are rendered such that a pixel density per subtended area is constant across the user's field of view.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: January 28, 2020
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Michael Mantor, Laurent Lefebvre, Mika Tuomi, Kiia Kallio
  • Publication number: 20190122417
    Abstract: A system, method and a non-transitory computer readable storage medium are provided for hybrid rendering with deferred primitive batch binning. A primitive batch is generated from one or more primitives. A bin is identified for processing the primitive batch. At least a portion of each primitive intersecting the identified bin is processed and a next bin for processing the primitive batch is identified based on an intercept walk order. The processing is iteratively repeated for the one or more primitives in the primitive batch for successive bins until all primitives of the primitive batch are completely processed. Then, the one or more primitives in the primitive batch are further processed.
    Type: Application
    Filed: November 2, 2018
    Publication date: April 25, 2019
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Michael Mantor, Laurent Lefebvre, Mark Fowler, Timothy Kelley, Mikko Alho, Mika Tuomi, Kiia Kallio, Patrick Klas Rudolf Buss, Jari Antero Komppa, Kaj Tuomi
  • Patent number: 10169906
    Abstract: A system, method and a computer program product are provided for hybrid rendering with deferred primitive batch binning. A primitive batch is generated from a sequence of primitives. Initial bin intercepts are identified for primitives in the primitive batch. A bin for processing is identified. The bin corresponds to a region of a screen space. Pixels of the primitives intercepting the identified bin are processed. Next bin intercepts are identified while the primitives intercepting the identified bin are processed.
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: January 1, 2019
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Michael Mantor, Laurent Lefebvre, Mark Fowler, Timothy Kelley, Mikko Alho, Mika Tuomi, Kiia Kallio, Patrick Klas Rudolf Buss, Jari Antero Komppa, Kaj Tuomi
  • Publication number: 20180276790
    Abstract: An apparatus, such as a head mounted device (HMD), includes one or more processors configured to implement a graphics pipeline that renders pixels in window space with a nonuniform pixel spacing. The apparatus also includes a first distortion function that maps the non-uniformly spaced pixels in window space to uniformly spaced pixels in raster space. The apparatus further includes a scan converter configured to sample the pixels in window space through the first distortion function. The scan converter is configured to render display pixels used to generate an image for display to a user based on the uniformly spaced pixels in raster space. In some cases, the pixels in the window space are rendered such that a pixel density per subtended area is constant across the user's field of view.
    Type: Application
    Filed: December 15, 2017
    Publication date: September 27, 2018
    Inventors: Michael MANTOR, Laurent LEFEBVRE, Mika TUOMI, Kiia KALLIO
  • Publication number: 20180165872
    Abstract: Techniques for removing or identifying overlapping fragments in a fragment stream after z-culling are disclosed. The techniques include maintaining a first-in-first-out buffer that stores post-z-cull fragments. Each time a new fragment is received at the buffer, the screen position of the fragment is checked against all other fragments in the buffer. If the screen position of the fragment matches the screen position of a fragment in the buffer, then the fragment in the buffer is removed or marked as overlapping. If the screen position of the fragment does not match the screen position of any fragment in the buffer, then no modification is performed to fragments already in the buffer. In either case, he fragment is added to the buffer. The contents of the buffer are transmitted to the pixel shader for pixel shading at a later time.
    Type: Application
    Filed: December 9, 2016
    Publication date: June 14, 2018
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Laurent Lefebvre, Michael Mantor, Mark Fowler, Mikko Alho, Mika Tuomi, Kiia Kallio, Patrick Klas Rudolf Buss, Jari Antero Komppa, Kaj Tuomi, Christopher J. Brennan
  • Publication number: 20160371873
    Abstract: A system, method and a computer program product are provided for hybrid rendering with deferred primitive batch binning A primitive batch is generated from a sequence of primitives. Initial bin intercepts are identified for primitives in the primitive batch. A bin for processing is identified. The bin corresponds to a region of a screen space. Pixels of the primitives intercepting the identified bin are processed. Next bin intercepts are identified while the primitives intercepting the identified bin are processed.
    Type: Application
    Filed: August 29, 2016
    Publication date: December 22, 2016
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Michael Mantor, Laurent Lefebvre, Mikko Alho, Mika Tuomi, Kiia Kallio
  • Publication number: 20140292756
    Abstract: A system, method and a computer program product are provided for hybrid rendering with deferred primitive batch binning. A primitive batch is generated from a sequence of primitives. Initial bin intercepts are identified for primitives in the primitive batch. A bin for processing is identified. The bin corresponds to a region of a screen space. Pixels of the primitives intercepting the identified bin are processed. Next bin intercepts are identified while the primitives intercepting the identified bin are processed.
    Type: Application
    Filed: March 29, 2013
    Publication date: October 2, 2014
    Applicants: ATI Technologies ULC, Advanced Micro Devices, Inc.
    Inventors: Michael MANTOR, Laurent Lefebvre, Mark Fowler, Timothy Kelley, Mikko Alho, Mika Tuomi, Kallio Kia, Patrick Klas Rudolf Buss, Jari Antero Komppa, Kaj Tuomi
  • Patent number: 8471862
    Abstract: An efficient rendering method for processing computer graphics in tiles. First a frame of data, typically at least one polygon, is received for rendering. While rendering a polygon the tile for the polygon is assigned so that it minimizes the number of the tiles needed for processing the polygon. It is possible to compute an offset value between the static tiles and the assigned tiles. If the offset value is computed, the rendering into an actual screen may be based on that.
    Type: Grant
    Filed: March 9, 2007
    Date of Patent: June 25, 2013
    Assignee: ATI Technologies ULC
    Inventor: Mika Tuomi
  • Patent number: 8390634
    Abstract: A graphics processor or a graphics block for use in a processor includes a type buffer used for determining if a currently processed pixel requires further processing. Each pixel has a number of sub-pixels and each sub-pixel line includes at least one counter that is stored in an edge buffer. A limited edge buffer that can store edge buffer values in a limited range can be employed. Each buffer can include information regarding the whole screen or a portion of thereof. The edge buffer also can be an external or internal buffer, and when implemented internally, the graphics processor or graphics block need not employ a bi-directional bus.
    Type: Grant
    Filed: January 31, 2007
    Date of Patent: March 5, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Mika Tuomi
  • Patent number: 8294731
    Abstract: A graphics processor or a graphics block for use in a processor includes a type buffer used for determining if a currently processed pixel requires further processing. Each pixel has a number of sub-pixels and each sub-pixel line includes at least one counter that is stored in an edge buffer. A limited edge buffer that can store edge buffer values in a limited range can be employed. Each buffer can include information regarding the whole screen or a portion of thereof. The edge buffer also can be an external or internal buffer, and when implemented internally, the graphics processor or graphics block need not employ a bi-directional bus.
    Type: Grant
    Filed: November 15, 2005
    Date of Patent: October 23, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Mika Tuomi
  • Patent number: 8269788
    Abstract: A processor unit that can be used in a handheld device and configured for anti-aliasing of a vector graphics image, and including a counter value calculator configured to calculate, for one edge at a time and pixel-by-pixel, counter values for each pixel in a rasterization direction, a counter value recorder configured to store the calculated counter values in an edge buffer, and a pixel coverage value calculator configured to calculate pixel coverage values based on the stored counter values. The calculated pixel coverage values can be utilized for anti-aliasing the vector graphics image, while rasterizing the vector graphics image.
    Type: Grant
    Filed: November 15, 2005
    Date of Patent: September 18, 2012
    Assignee: Advanced Micro Devices Inc.
    Inventor: Mika Tuomi
  • Patent number: 8159440
    Abstract: A controller/driver is composed of a work memory, a graphic engine, a display memory, and a driver circuit. The graphic engine converts externally received image data into first bitmap data, and stores the first bitmap data in the work memory. The display memory receives and stores second bitmap data developed from the first bitmap data stored in the work memory. The driver circuit drives a display panel in response to the second bitmap data received from the display memory.
    Type: Grant
    Filed: June 28, 2004
    Date of Patent: April 17, 2012
    Assignees: Advanced Micro Devices, Inc., Renesas Electronics Corporation
    Inventors: Hirobumi Furihata, Katsuhisa Oohashi, Junyou Shioda, Yoshiyuki Teshirogi, Takashi Nose, Mika Tuomi
  • Publication number: 20090033671
    Abstract: A method and device for enhanced rendering providing reduced memory bandwidth requirements in a graphics processor. In the rendering process, a classification buffer of limited bit length is used for classifying the pixels. Based on the classification, a decision on the pixel color may be made without accessing the multi-sample buffer for a portion of the pixels. This reduces the memory bandwidth requirements.
    Type: Application
    Filed: August 2, 2007
    Publication date: February 5, 2009
    Applicant: ATI Technologies ULC
    Inventors: Mika Tuomi, Kiia Kallio, Jarno Paananen