Patents by Inventor Mika Tuomi
Mika Tuomi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240135626Abstract: A method, computer system, and a non-transitory computer-readable storage medium for performing primitive batch binning are disclosed. The method, computer system, and non-transitory computer-readable storage medium include techniques for generating a primitive batch from a plurality of primitives, computing respective bin intercepts for each of the plurality of primitives in the primitive batch, and shading the primitive batch by iteratively processing each of the respective bin intercepts computed until all of the respective bin intercepts are processed.Type: ApplicationFiled: January 2, 2024Publication date: April 25, 2024Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Michael Mantor, Laurent Lefebvre, Mark Fowler, Timothy Kelley, Mikko Alho, Mika Tuomi, Kiia Kallio, Patrick Klas Rudolf Buss, Jari Antero Komppa, Kaj Tuomi
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Patent number: 11954782Abstract: A method, system, and non-transitory computer readable storage medium for rasterizing primitives are disclosed. The method, system, and non-transitory computer readable storage medium includes: generating a primitive batch from a sequence of one or more primitives, wherein the primitive batch includes primitives sorted into one or more row groups based on which row of a plurality of rows each primitive intersects; and processing each row group, the processing for each row group including: identifying one or more primitive column intercepts for each of the one or more primitives in the row group, wherein each combination of primitive column intercept and row identifies a bin; and rasterizing the one or more primitives that intersect the bin.Type: GrantFiled: March 22, 2021Date of Patent: April 9, 2024Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Michael Mantor, Laurent Lefebvre, Mikko Alho, Mika Tuomi, Kiia Kallio
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Publication number: 20240104685Abstract: Devices and methods method of tiled rendering are provided which comprises dividing a frame to be rendered, into a plurality of tiles, receiving commands to execute a plurality of subpasses of the tiles, interleaving execution of same subpasses of multiple tiles of the frame by executing one or more subpasses as skip operations, storing visibility data, for subsequently ordered subpasses of the tiles, at memory addresses allocated for data of corresponding adjacent tiles in a first direction of traversal and rendering the tiles for the subsequently ordered subpasses using the visibility data stored at the memory addresses allocated for corresponding adjacent tiles in a second direction of traversal, opposite the first direction of traversal.Type: ApplicationFiled: September 28, 2022Publication date: March 28, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Ruijin Wu, Michael John Livesley, Kiia Kallio, Jan H. Achrenius, Mika Tuomi
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Patent number: 11880924Abstract: A method of tiled rendering is provided which comprises dividing a frame to be rendered, into a plurality of tiles, receiving commands to execute a plurality of subpasses of the tiles and interleaving execution of same subpasses of multiple tiles of the frame. Interleaving execution of same subpasses of multiple tiles comprises executing a previously ordered first subpass of a second tile between execution of the previously ordered first subpass of a first tile and execution of a subsequently ordered second subpass of the first tile. The interleaving is performed, for example, by executing the plurality of subpasses in an order different from the order in which the commands to execute the plurality of subpasses are stored and issued. Alternatively, interleaving is performed by executing one or more subpasses as skip operations such that the plurality of subpasses are executed in the same order.Type: GrantFiled: December 29, 2021Date of Patent: January 23, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Ruijin Wu, Mika Tuomi, Paavo Sampo Ilmari Pessi, Anirudh R. Acharya
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Patent number: 11880926Abstract: A method, computer system, and a non-transitory computer-readable storage medium for performing primitive batch binning are disclosed. The method, computer system, and non-transitory computer-readable storage medium include techniques for generating a primitive batch from a plurality of primitives, computing respective bin intercepts for each of the plurality of primitives in the primitive batch, and shading the primitive batch by iteratively processing each of the respective bin intercepts computed until all of the respective bin intercepts are processed.Type: GrantFiled: May 16, 2022Date of Patent: January 23, 2024Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Michael Mantor, Laurent Lefebvre, Mark Fowler, Timothy Kelley, Mikko Alho, Mika Tuomi, Kiia Kallio, Patrick Klas Rudolf Buss, Jari Antero Komppa, Kaj Tuomi
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Patent number: 11741653Abstract: A method of tiled rendering of an image for display is provided which comprises receiving an image comprising one or more three dimensional (3D) objects and executing a visibility pass for determining locations of primitives of the image. The method also comprises executing, concurrently with the executing of the visibility pass, front end geometry processing of one of the primitives determined, from the visibility pass, to be in a first one of a plurality of tiles of the image and executing, concurrently with the executing of the visibility pass, back end processing of the one primitive in the first tile.Type: GrantFiled: July 28, 2020Date of Patent: August 29, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Mika Tuomi, Ruijin Wu, Anirudh R. Acharya, Kiia Kallio
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Publication number: 20230205698Abstract: A processing system divides successive dispatches of work items into portions. The successive dispatches are separated from each other by barriers, each barrier indicating that the work items of the previous dispatch must complete execution before work items of a subsequent dispatch can begin execution. In some embodiments, the processing system interleaves execution of portions of a first dispatch with portions of subsequent dispatches that consume data produced by the first dispatch. The processing system thereby reduces the amount of data written to the local cache by a producer dispatch while preserving data locality for a subsequent consumer (or consumer/producer) dispatch and facilitating processing efficiency.Type: ApplicationFiled: December 29, 2021Publication date: June 29, 2023Inventors: Saurabh SHARMA, Hashem HASHEMI, Paavo PESSI, Mika TUOMI, Gianpaolo TOMMASI, Jeremy LUKACS, Guennadi RIGUER
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Patent number: 11631187Abstract: Systems, apparatuses, and methods for implementing a depth buffer pre-pass are disclosed. A rendering application uses a binning approach to render primitives of a virtual scene on a tile-by-tile basis, with each tile corresponding to a portion of the screen. The application causes a depth buffer pre-pass to be performed for the primitives of the tile before a pixel shader is invoked. During the depth buffer pre-pass, only the depth part of the virtual scene is rendered to determine which pixel samples are visible and which pixel samples are hidden. Then, the scene is redrawn, but the pixel samples that are hidden are not sent to the pixel shader. In cases where a relatively large percentage of primitives overlap, this technique increases the efficiency of the rendering application since pixel shading can be avoided for the pixel samples that are hidden.Type: GrantFiled: September 24, 2020Date of Patent: April 18, 2023Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Jan Henrik Achrenius, Mika Tuomi, Kiia Kallio, Pazhani Pillai, Laurent Lefebvre
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Patent number: 11551398Abstract: Systems, apparatuses, and methods for implementing light volume rendering techniques are disclosed. A processor is coupled to a memory. A processor renders the geometry of a scene into a geometry buffer. For a given light source in the scene, the processor initiates two shader pipeline passes to determine which pixels in the geometry buffer to light. On the first pass, the processor renders a front-side of a light volume corresponding to the light source. Any pixels of the geometry buffer which are in front of the front-side of the light volume are marked as pixels to be discarded. Then, during the second pass, only those pixels which were not marked to be discarded are sent to the pixel shader. This approach helps to reduce the overhead involved in applying a lighting effect to the scene by reducing the amount of work performed by the pixel shader.Type: GrantFiled: August 31, 2020Date of Patent: January 10, 2023Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Mika Tuomi, Miikka Petteri Kangasluoma, Jan Henrik Achrenius, Laurent Lefebvre
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Publication number: 20220319091Abstract: A method and apparatus of tile rendering of an image for a display in a computer system includes receiving the image in a graphics pipeline of the computer system, the image comprising one or more three dimensional (3D) objects. The image is divided into one or more tiles. A depth test is performed on the one or more tiles, and based upon the depth test, visibility information of the one or more tiles is binned.Type: ApplicationFiled: December 27, 2021Publication date: October 6, 2022Applicant: Advanced Micro Devices, Inc.Inventors: Mika Tuomi, Ruijin Wu, Anirudh R. Acharya
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Publication number: 20220309729Abstract: A method of tiled rendering is provided which comprises dividing a frame to be rendered, into a plurality of tiles, receiving commands to execute a plurality of subpasses of the tiles and interleaving execution of same subpasses of multiple tiles of the frame. Interleaving execution of same subpasses of multiple tiles comprises executing a previously ordered first subpass of a second tile between execution of the previously ordered first subpass of a first tile and execution of a subsequently ordered second subpass of the first tile. The interleaving is performed, for example, by executing the plurality of subpasses in an order different from the order in which the commands to execute the plurality of subpasses are stored and issued. Alternatively, interleaving is performed by executing one or more subpasses as skip operations such that the plurality of subpasses are executed in the same order.Type: ApplicationFiled: December 29, 2021Publication date: September 29, 2022Applicant: Advanced Micro Devices, Inc.Inventors: Ruijin Wu, Mika Tuomi, Paavo Sampo Ilmari Pessi, Anirudh R. Acharya
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Publication number: 20220277508Abstract: A method, computer system, and a non-transitory computer-readable storage medium for performing primitive batch binning are disclosed. The method, computer system, and non-transitory computer-readable storage medium include techniques for generating a primitive batch from a plurality of primitives, computing respective bin intercepts for each of the plurality of primitives in the primitive batch, and shading the primitive batch by iteratively processing each of the respective bin intercepts computed until all of the respective bin intercepts are processed.Type: ApplicationFiled: May 16, 2022Publication date: September 1, 2022Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Michael Mantor, Laurent Lefebvre, Mark Fowler, Timothy Kelley, Mikko Alho, Mika Tuomi, Kiia Kallio, Patrick Klas Rudolf Buss, Jari Antero Komppa, Kaj Tuomi
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Patent number: 11335052Abstract: A system, method and a non-transitory computer readable storage medium are provided for hybrid rendering with deferred primitive batch binning. A primitive batch is generated from one or more primitives. A bin is identified for processing the primitive batch. At least a portion of each primitive intersecting the identified bin is processed and a next bin for processing the primitive batch is identified based on an intercept walk order. The processing is iteratively repeated for the one or more primitives in the primitive batch for successive bins until all primitives of the primitive batch are completely processed. Then, the one or more primitives in the primitive batch are further processed.Type: GrantFiled: November 2, 2018Date of Patent: May 17, 2022Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Michael Mantor, Laurent Lefebvre, Mark Fowler, Timothy Kelley, Mikko Alho, Mika Tuomi, Kiia Kallio, Patrick Klas Rudolf Buss, Jari Antero Komppa, Kaj Tuomi
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Publication number: 20220092801Abstract: Systems, apparatuses, and methods for implementing a depth buffer pre-pass are disclosed. A rendering application uses a binning approach to render primitives of a virtual scene on a tile-by-tile basis, with each tile corresponding to a portion of the screen. The application causes a depth buffer pre-pass to be performed for the primitives of the tile before a pixel shader is invoked. During the depth buffer pre-pass, only the depth part of the virtual scene is rendered to determine which pixel samples are visible and which pixel samples are hidden. Then, the scene is redrawn, but the pixel samples that are hidden are not sent to the pixel shader. In cases where a relatively large percentage of primitives overlap, this technique increases the efficiency of the rendering application since pixel shading can be avoided for the pixel samples that are hidden.Type: ApplicationFiled: September 24, 2020Publication date: March 24, 2022Inventors: Jan Henrik Achrenius, Mika Tuomi, Kiia Kallio, Pazhani Pillai, Laurent Lefebvre
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Publication number: 20220036629Abstract: A method of tiled rendering of an image for display is provided which comprises receiving an image comprising one or more three dimensional (3D) objects and executing a visibility pass for determining locations of primitives of the image. The method also comprises executing, concurrently with the executing of the visibility pass, front end geometry processing of one of the primitives determined, from the visibility pass, to be in a first one of a plurality of tiles of the image and executing, concurrently with the executing of the visibility pass, back end processing of the one primitive in the first tile.Type: ApplicationFiled: July 28, 2020Publication date: February 3, 2022Applicant: Advanced Micro Devices, Inc.Inventors: Mika Tuomi, Ruijin Wu, Anirudh R. Acharya, Kiia Kallio
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Publication number: 20210398325Abstract: Methods, devices, and systems for compressing and decompressing a stream of indices associated with graphics primitives. A group of delta values is determined based on a group of indices of the stream of indices. The group of delta values is compared to delta values in a lookup table. The group of indices is compressed based on an entry in the lookup table if the group of delta values matches all delta values in the entry, otherwise, the group of indices is compressed based on variable-length encoding.Type: ApplicationFiled: February 26, 2021Publication date: December 23, 2021Applicant: Advanced Micro Devices, Inc.Inventors: Kiia Kallio, Mika Tuomi, Ruijin Wu, Anirudh R. Acharya
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Publication number: 20210287418Abstract: A processor dynamically selects a render mode for each render pass of a frame based on the characteristics of the render pass. A software driver of the processor receives graphics operations from an application executing at the processor and converts the graphics operations into a command stream that is provided to the graphics pipeline. As the driver converts the graphics operations into the command stream, the driver analyzes each render pass of the frame to determine characteristics of the render passes, and selects a render mode for each render pass based on the characteristics of the render pass.Type: ApplicationFiled: August 31, 2020Publication date: September 16, 2021Inventors: Anirudh R. ACHARYA, Ruijin WU, Young In YEO, Mika TUOMI, Kiia KALLIO
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Publication number: 20210225060Abstract: A processing device and a method of tiled rendering of an image for display is provided. The processing device includes memory and a processor. The processor is configured to receive the image comprising one or more three dimensional (3D) objects, divide the image into tiles, execute coarse level tiling for the tiles of the image and execute fine level tiling for the tiles of the image. The processing device also includes same fixed function hardware used to execute the coarse level tiling and the fine level tiling. The processor is also configured to determine visibility information for a first one of the tiles. The visibility information is divided into draw call visibility information and triangle visibility information for each remaining tile of the image.Type: ApplicationFiled: September 25, 2020Publication date: July 22, 2021Applicant: Advanced Micro Devices, Inc.Inventors: Mika Tuomi, Kiia Kallio, Ruijin Wu, Anirudh R. Acharya, Vineet Goel
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Publication number: 20210209831Abstract: A method, system, and non-transitory computer readable storage medium for rasterizing primitives are disclosed. The method, system, and non-transitory computer readable storage medium includes: generating a primitive batch from a sequence of one or more primitives, wherein the primitive batch includes primitives sorted into one or more row groups based on which row of a plurality of rows each primitive intersects; and processing each row group, the processing for each row group including: identifying one or more primitive column intercepts for each of the one or more primitives in the row group, wherein each combination of primitive column intercept and row identifies a bin; and rasterizing the one or more primitives that intersect the bin.Type: ApplicationFiled: March 22, 2021Publication date: July 8, 2021Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Michael Mantor, Laurent Lefebvre, Mikko Alho, Mika Tuomi, Kiia Kallio
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Publication number: 20210150797Abstract: Systems, apparatuses, and methods for implementing light volume rendering techniques are disclosed. A processor is coupled to a memory. A processor renders the geometry of a scene into a geometry buffer. For a given light source in the scene, the processor initiates two shader pipeline passes to determine which pixels in the geometry buffer to light. On the first pass, the processor renders a front-side of a light volume corresponding to the light source. Any pixels of the geometry buffer which are in front of the front-side of the light volume are marked as pixels to be discarded. Then, during the second pass, only those pixels which were not marked to be discarded are sent to the pixel shader. This approach helps to reduce the overhead involved in applying a lighting effect to the scene by reducing the amount of work performed by the pixel shader.Type: ApplicationFiled: August 31, 2020Publication date: May 20, 2021Inventors: Mika Tuomi, Miikka Petteri Kangasluoma, Jan Henrik Achrenius, Laurent Lefebvre