Patents by Inventor Mika Tuomi
Mika Tuomi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210150797Abstract: Systems, apparatuses, and methods for implementing light volume rendering techniques are disclosed. A processor is coupled to a memory. A processor renders the geometry of a scene into a geometry buffer. For a given light source in the scene, the processor initiates two shader pipeline passes to determine which pixels in the geometry buffer to light. On the first pass, the processor renders a front-side of a light volume corresponding to the light source. Any pixels of the geometry buffer which are in front of the front-side of the light volume are marked as pixels to be discarded. Then, during the second pass, only those pixels which were not marked to be discarded are sent to the pixel shader. This approach helps to reduce the overhead involved in applying a lighting effect to the scene by reducing the amount of work performed by the pixel shader.Type: ApplicationFiled: August 31, 2020Publication date: May 20, 2021Inventors: Mika Tuomi, Miikka Petteri Kangasluoma, Jan Henrik Achrenius, Laurent Lefebvre
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Patent number: 10957094Abstract: A system, method and a computer program product are provided for hybrid rendering with deferred primitive batch binning A primitive batch is generated from a sequence of primitives. Initial bin intercepts are identified for primitives in the primitive batch. A bin for processing is identified. The bin corresponds to a region of a screen space. Pixels of the primitives intercepting the identified bin are processed. Next bin intercepts are identified while the primitives intercepting the identified bin are processed.Type: GrantFiled: August 29, 2016Date of Patent: March 23, 2021Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Michael Mantor, Laurent Lefebvre, Mikko Alho, Mika Tuomi, Kiia Kallio
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Patent number: 10943389Abstract: Techniques for removing or identifying overlapping fragments in a fragment stream after z-culling are disclosed. The techniques include maintaining a first-in-first-out buffer that stores post-z-cull fragments. Each time a new fragment is received at the buffer, the screen position of the fragment is checked against all other fragments in the buffer. If the screen position of the fragment matches the screen position of a fragment in the buffer, then the fragment in the buffer is removed or marked as overlapping. If the screen position of the fragment does not match the screen position of any fragment in the buffer, then no modification is performed to fragments already in the buffer. In either case, he fragment is added to the buffer. The contents of the buffer are transmitted to the pixel shader for pixel shading at a later time.Type: GrantFiled: December 9, 2016Date of Patent: March 9, 2021Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Laurent Lefebvre, Michael Mantor, Mark Fowler, Mikko Alho, Mika Tuomi, Kiia Kallio, Patrick Klas Rudolf Buss, Jari Antero Komppa, Kaj Tuomi, Christopher J. Brennan
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Patent number: 10546365Abstract: An apparatus, such as a head mounted device (HMD), includes one or more processors configured to implement a graphics pipeline that renders pixels in window space with a nonuniform pixel spacing. The apparatus also includes a first distortion function that maps the non-uniformly spaced pixels in window space to uniformly spaced pixels in raster space. The apparatus further includes a scan converter configured to sample the pixels in window space through the first distortion function. The scan converter is configured to render display pixels used to generate an image for display to a user based on the uniformly spaced pixels in raster space. In some cases, the pixels in the window space are rendered such that a pixel density per subtended area is constant across the user's field of view.Type: GrantFiled: December 15, 2017Date of Patent: January 28, 2020Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Michael Mantor, Laurent Lefebvre, Mika Tuomi, Kiia Kallio
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Publication number: 20190122417Abstract: A system, method and a non-transitory computer readable storage medium are provided for hybrid rendering with deferred primitive batch binning. A primitive batch is generated from one or more primitives. A bin is identified for processing the primitive batch. At least a portion of each primitive intersecting the identified bin is processed and a next bin for processing the primitive batch is identified based on an intercept walk order. The processing is iteratively repeated for the one or more primitives in the primitive batch for successive bins until all primitives of the primitive batch are completely processed. Then, the one or more primitives in the primitive batch are further processed.Type: ApplicationFiled: November 2, 2018Publication date: April 25, 2019Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Michael Mantor, Laurent Lefebvre, Mark Fowler, Timothy Kelley, Mikko Alho, Mika Tuomi, Kiia Kallio, Patrick Klas Rudolf Buss, Jari Antero Komppa, Kaj Tuomi
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Patent number: 10169906Abstract: A system, method and a computer program product are provided for hybrid rendering with deferred primitive batch binning. A primitive batch is generated from a sequence of primitives. Initial bin intercepts are identified for primitives in the primitive batch. A bin for processing is identified. The bin corresponds to a region of a screen space. Pixels of the primitives intercepting the identified bin are processed. Next bin intercepts are identified while the primitives intercepting the identified bin are processed.Type: GrantFiled: March 29, 2013Date of Patent: January 1, 2019Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Michael Mantor, Laurent Lefebvre, Mark Fowler, Timothy Kelley, Mikko Alho, Mika Tuomi, Kiia Kallio, Patrick Klas Rudolf Buss, Jari Antero Komppa, Kaj Tuomi
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Publication number: 20180276790Abstract: An apparatus, such as a head mounted device (HMD), includes one or more processors configured to implement a graphics pipeline that renders pixels in window space with a nonuniform pixel spacing. The apparatus also includes a first distortion function that maps the non-uniformly spaced pixels in window space to uniformly spaced pixels in raster space. The apparatus further includes a scan converter configured to sample the pixels in window space through the first distortion function. The scan converter is configured to render display pixels used to generate an image for display to a user based on the uniformly spaced pixels in raster space. In some cases, the pixels in the window space are rendered such that a pixel density per subtended area is constant across the user's field of view.Type: ApplicationFiled: December 15, 2017Publication date: September 27, 2018Inventors: Michael MANTOR, Laurent LEFEBVRE, Mika TUOMI, Kiia KALLIO
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Publication number: 20180165872Abstract: Techniques for removing or identifying overlapping fragments in a fragment stream after z-culling are disclosed. The techniques include maintaining a first-in-first-out buffer that stores post-z-cull fragments. Each time a new fragment is received at the buffer, the screen position of the fragment is checked against all other fragments in the buffer. If the screen position of the fragment matches the screen position of a fragment in the buffer, then the fragment in the buffer is removed or marked as overlapping. If the screen position of the fragment does not match the screen position of any fragment in the buffer, then no modification is performed to fragments already in the buffer. In either case, he fragment is added to the buffer. The contents of the buffer are transmitted to the pixel shader for pixel shading at a later time.Type: ApplicationFiled: December 9, 2016Publication date: June 14, 2018Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Laurent Lefebvre, Michael Mantor, Mark Fowler, Mikko Alho, Mika Tuomi, Kiia Kallio, Patrick Klas Rudolf Buss, Jari Antero Komppa, Kaj Tuomi, Christopher J. Brennan
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Publication number: 20160371873Abstract: A system, method and a computer program product are provided for hybrid rendering with deferred primitive batch binning A primitive batch is generated from a sequence of primitives. Initial bin intercepts are identified for primitives in the primitive batch. A bin for processing is identified. The bin corresponds to a region of a screen space. Pixels of the primitives intercepting the identified bin are processed. Next bin intercepts are identified while the primitives intercepting the identified bin are processed.Type: ApplicationFiled: August 29, 2016Publication date: December 22, 2016Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Michael Mantor, Laurent Lefebvre, Mikko Alho, Mika Tuomi, Kiia Kallio
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Publication number: 20140292756Abstract: A system, method and a computer program product are provided for hybrid rendering with deferred primitive batch binning. A primitive batch is generated from a sequence of primitives. Initial bin intercepts are identified for primitives in the primitive batch. A bin for processing is identified. The bin corresponds to a region of a screen space. Pixels of the primitives intercepting the identified bin are processed. Next bin intercepts are identified while the primitives intercepting the identified bin are processed.Type: ApplicationFiled: March 29, 2013Publication date: October 2, 2014Applicants: ATI Technologies ULC, Advanced Micro Devices, Inc.Inventors: Michael MANTOR, Laurent Lefebvre, Mark Fowler, Timothy Kelley, Mikko Alho, Mika Tuomi, Kallio Kia, Patrick Klas Rudolf Buss, Jari Antero Komppa, Kaj Tuomi
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Patent number: 8471862Abstract: An efficient rendering method for processing computer graphics in tiles. First a frame of data, typically at least one polygon, is received for rendering. While rendering a polygon the tile for the polygon is assigned so that it minimizes the number of the tiles needed for processing the polygon. It is possible to compute an offset value between the static tiles and the assigned tiles. If the offset value is computed, the rendering into an actual screen may be based on that.Type: GrantFiled: March 9, 2007Date of Patent: June 25, 2013Assignee: ATI Technologies ULCInventor: Mika Tuomi
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Patent number: 8390634Abstract: A graphics processor or a graphics block for use in a processor includes a type buffer used for determining if a currently processed pixel requires further processing. Each pixel has a number of sub-pixels and each sub-pixel line includes at least one counter that is stored in an edge buffer. A limited edge buffer that can store edge buffer values in a limited range can be employed. Each buffer can include information regarding the whole screen or a portion of thereof. The edge buffer also can be an external or internal buffer, and when implemented internally, the graphics processor or graphics block need not employ a bi-directional bus.Type: GrantFiled: January 31, 2007Date of Patent: March 5, 2013Assignee: Advanced Micro Devices, Inc.Inventor: Mika Tuomi
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Patent number: 8294731Abstract: A graphics processor or a graphics block for use in a processor includes a type buffer used for determining if a currently processed pixel requires further processing. Each pixel has a number of sub-pixels and each sub-pixel line includes at least one counter that is stored in an edge buffer. A limited edge buffer that can store edge buffer values in a limited range can be employed. Each buffer can include information regarding the whole screen or a portion of thereof. The edge buffer also can be an external or internal buffer, and when implemented internally, the graphics processor or graphics block need not employ a bi-directional bus.Type: GrantFiled: November 15, 2005Date of Patent: October 23, 2012Assignee: Advanced Micro Devices, Inc.Inventor: Mika Tuomi
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Patent number: 8269788Abstract: A processor unit that can be used in a handheld device and configured for anti-aliasing of a vector graphics image, and including a counter value calculator configured to calculate, for one edge at a time and pixel-by-pixel, counter values for each pixel in a rasterization direction, a counter value recorder configured to store the calculated counter values in an edge buffer, and a pixel coverage value calculator configured to calculate pixel coverage values based on the stored counter values. The calculated pixel coverage values can be utilized for anti-aliasing the vector graphics image, while rasterizing the vector graphics image.Type: GrantFiled: November 15, 2005Date of Patent: September 18, 2012Assignee: Advanced Micro Devices Inc.Inventor: Mika Tuomi
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Patent number: 8159440Abstract: A controller/driver is composed of a work memory, a graphic engine, a display memory, and a driver circuit. The graphic engine converts externally received image data into first bitmap data, and stores the first bitmap data in the work memory. The display memory receives and stores second bitmap data developed from the first bitmap data stored in the work memory. The driver circuit drives a display panel in response to the second bitmap data received from the display memory.Type: GrantFiled: June 28, 2004Date of Patent: April 17, 2012Assignees: Advanced Micro Devices, Inc., Renesas Electronics CorporationInventors: Hirobumi Furihata, Katsuhisa Oohashi, Junyou Shioda, Yoshiyuki Teshirogi, Takashi Nose, Mika Tuomi
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Publication number: 20090033671Abstract: A method and device for enhanced rendering providing reduced memory bandwidth requirements in a graphics processor. In the rendering process, a classification buffer of limited bit length is used for classifying the pixels. Based on the classification, a decision on the pixel color may be made without accessing the multi-sample buffer for a portion of the pixels. This reduces the memory bandwidth requirements.Type: ApplicationFiled: August 2, 2007Publication date: February 5, 2009Applicant: ATI Technologies ULCInventors: Mika Tuomi, Kiia Kallio, Jarno Paananen
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Publication number: 20080218521Abstract: An efficient rendering method for processing computer graphics in tiles. First a frame of data, typically at least one polygon, is received for rendering. While rendering a polygon the tile for the polygon is assigned so that it minimizes the number of the tiles needed for processing the polygon. It is possible to compute an offset value between the static tiles and the assigned tiles. If the offset value is computed, the rendering into an actual screen may be based on that.Type: ApplicationFiled: March 9, 2007Publication date: September 11, 2008Applicant: ATI Technologies ULCInventor: Mika Tuomi
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Publication number: 20070132775Abstract: A graphics processor or a graphics block for use in a processor includes a type buffer used for determining if a currently processed pixel requires further processing. Each pixel has a number of sub-pixels and each sub-pixel line includes at least one counter that is stored in an edge buffer. A limited edge buffer that can store edge buffer values in a limited range can be employed. Each buffer can include information regarding the whole screen or a portion of thereof. The edge buffer also can be an external or internal buffer, and when implemented internally, the graphics processor or graphics block need not employ a bi-directional bus.Type: ApplicationFiled: January 31, 2007Publication date: June 14, 2007Inventor: Mika Tuomi
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Publication number: 20070109309Abstract: A graphics processor or a graphics block for use in a processor includes a type buffer used for determining if a currently processed pixel requires further processing. Each pixel has a number of sub-pixels and each sub-pixel line includes at least one counter that is stored in an edge buffer. A limited edge buffer that can store edge buffer values in a limited range can be employed. Each buffer can include information regarding the whole screen or a portion of thereof. The edge buffer also can be an external or internal buffer, and when implemented internally, the graphics processor or graphics block need not employ a bi-directional bus.Type: ApplicationFiled: November 15, 2005Publication date: May 17, 2007Applicant: Bitboys OyInventor: Mika Tuomi
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Publication number: 20070109318Abstract: A processor unit that can be used in a handheld device and configured for anti-aliasing of a vector graphics image, and including a counter value calculator configured to calculate, for one edge at a time and pixel-by-pixel, counter values for each pixel in a rasterization direction, a counter value recorder configured to store the calculated counter values in an edge buffer, and a pixel coverage value calculator configured to calculate pixel coverage values based on the stored counter values. The calculated pixel coverage values can be utilized for anti-aliasing the vector graphics image, while rasterizing the vector graphics image.Type: ApplicationFiled: November 15, 2005Publication date: May 17, 2007Applicant: Bitboys OyInventor: Mika Tuomi