Patents by Inventor Mike Connell

Mike Connell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8461685
    Abstract: A substrate including a plurality of integrated circuitry die is fabricated or otherwise provided. The individual die have bond pads. A passivation layer comprising a silicone material is formed over the bond pads. Openings are formed through the silicone material to the bond pads. After the openings are formed, the die are singulated from the substrate. In one implementation, a method of fabricating integrated circuitry includes providing a substrate comprising a plurality of integrated circuitry die. Individual of the die have bond pads. A first blanket passivation layer is formed over the substrate in contact with the bond pads. A different second blanket passivation layer comprising silicone material is formed over the first passivation layer. Openings are formed through the first and second passivation layers to the bond pads. After the openings are formed, the die are singulated from the substrate. Other aspects and implementations are contemplated.
    Type: Grant
    Filed: October 4, 2005
    Date of Patent: June 11, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Tongbi Jiang, Mike Connell
  • Patent number: 7537966
    Abstract: A method for fabricating a BOC package includes the steps of providing a semiconductor die having planarized bumps encapsulated in a polymer layer, and providing a substrate having a plurality of conductors and an opening. The method also includes the steps of attaching the die to the substrate in a BOC configuration, wire bonding wires through the opening to the conductors and the bumps, and forming a die encapsulant on the die.
    Type: Grant
    Filed: August 28, 2006
    Date of Patent: May 26, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Mike Connell, Tongbi Jiang
  • Patent number: 7510017
    Abstract: A device includes a main body adapted to couple between a first element of a working string and a second element of the working string. A seal is provided about the main body and is adapted to substantially sealingly engage a wall of the wellbore. An conductor is carried by the main body. The conductor is adapted to communicate at least one of electrical current or a light signal between an interior of the first element and the second element while the seal is substantially sealingly engaging the wall of the wellbore, while the device is released from sealingly engaging the wall of the wellbore, and/or both.
    Type: Grant
    Filed: November 9, 2006
    Date of Patent: March 31, 2009
    Assignee: Halliburton Energy Services, Inc.
    Inventors: Matt Howell, James C. Tucker, Mike Connell
  • Patent number: 7479413
    Abstract: A semiconductor package includes a substrate, a die attached and wire bonded to the substrate, and a die encapsulant encapsulating the die. The die includes a circuit side having a pattern of die contacts, planarized wire bonding contacts bonded to the die contacts, and a planarized polymer layer on the circuit side configured as stress defect barrier. A method for fabricating the package includes the steps of forming bumps on the die, encapsulating the bumps in a polymer layer, and then planarizing the polymer layer and the bumps to form the planarized wire bonding contacts. The method also includes the steps of attaching and wire bonding the die to the substrate, and then forming the die encapsulant on the die.
    Type: Grant
    Filed: October 3, 2005
    Date of Patent: January 20, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Mike Connell, Tongbi Jiang
  • Publication number: 20080110644
    Abstract: A device includes a main body adapted to couple between a first element of a working string and a second element of the working string. A seal is provided about the main body and is adapted to substantially sealingly engage a wall of the wellbore. An conductor is carried by the main body. The conductor is adapted to communicate at least one of electrical current or a light signal between an interior of the first element and the second element while the seal is substantially sealingly engaging the wall of the wellbore, while the device is released from sealingly engaging the wall of the wellbore, and/or both.
    Type: Application
    Filed: November 9, 2006
    Publication date: May 15, 2008
    Inventors: Matt Howell, James C. Tucker, Mike Connell
  • Patent number: 7170184
    Abstract: Methods are provided to improve the adhesive bonding of a semiconductor die to a substrate through an adhesive paste by forming a layer of silicon dioxide on the back surface of the semiconductor die prior to applying the adhesive paste. Contacting the semiconductor die with ozone, in a gas mixture or in a mixture with water provides rapid oxidation of the silicon layer at the back of the semiconductor die to a silicon dioxide layer of at least 10 angstroms thick, which is sufficient to greatly improve bonding to the adhesive. The formation of a silicon dioxide surface layer prior to application of the adhesive is particularly beneficial when combined with rapid, snap curing processes, where the adhesive can be reliably cured by heating the semiconductor die for less than about 1 minute.
    Type: Grant
    Filed: January 13, 2003
    Date of Patent: January 30, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Tongbi Jiang, Mike Connell, Li Li, Curtis Hollingshead
  • Publication number: 20060292752
    Abstract: A method for fabricating a BOC package includes the steps of providing a semiconductor die having planarized bumps encapsulated in a polymer layer, and providing a substrate having a plurality of conductors and an opening. The method also includes the steps of attaching the die to the substrate in a BOC configuration, wire bonding wires through the opening to the conductors and the bumps, and forming a die encapsulant on the die.
    Type: Application
    Filed: August 28, 2006
    Publication date: December 28, 2006
    Inventors: Mike Connell, Tongbi Jiang
  • Patent number: 7078267
    Abstract: A substrate including a plurality of integrated circuitry die is fabricated or otherwise provided. The individual die have bond pads. A passivation layer comprising a silicone material is formed over the bond pads. Openings are formed through the silicone material to the bond pads. After the openings are formed, the die are singulated from the substrate. In one implementation, a method of fabricating integrated circuitry includes providing a substrate comprising a plurality of integrated circuitry die. Individual of the die have bond pads. A first blanket passivation layer is formed over the substrate in contact with the bond pads. A different second blanket passivation layer comprising silicone material is formed over the first passivation layer. Openings are formed through the first and second passivation layers to the bond pads. After the openings are formed, the die are singulated from the substrate. Other aspects and implementations are contemplated.
    Type: Grant
    Filed: October 7, 2005
    Date of Patent: July 18, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Tongbi Jiang, Mike Connell
  • Publication number: 20060030077
    Abstract: A substrate including a plurality of integrated circuitry die is fabricated or otherwise provided. The individual die have bond pads. A passivation layer comprising a silicone material is formed over the bond pads. Openings are formed through the silicone material to the bond pads. After the openings are formed, the die are singulated from the substrate. In one implementation, a method of fabricating integrated circuitry includes providing a substrate comprising a plurality of integrated circuitry die. Individual of the die have bond pads. A first blanket passivation layer is formed over the substrate in contact with the bond pads. A different second blanket passivation layer comprising silicone material is formed over the first passivation layer. Openings are formed through the first and second passivation layers to the bond pads. After the openings are formed, the die are singulated from the substrate. Other aspects and implementations are contemplated.
    Type: Application
    Filed: October 4, 2005
    Publication date: February 9, 2006
    Inventors: Tongbi Jiang, Mike Connell
  • Publication number: 20060030081
    Abstract: A semiconductor package includes a substrate, a die attached and wire bonded to the substrate, and a die encapsulant encapsulating the die. The die includes a circuit side having a pattern of die contacts, planarized wire bonding contacts bonded to the die contacts, and a planarized polymer layer on the circuit side configured as stress defect barrier. A method for fabricating the package includes the steps of forming bumps on the die, encapsulating the bumps in a polymer layer, and then planarizing the polymer layer and the bumps to form the planarized wire bonding contacts. The method also includes the steps of attaching and wire bonding the die to the substrate, and then forming the die encapsulant on the die.
    Type: Application
    Filed: October 3, 2005
    Publication date: February 9, 2006
    Inventors: Mike Connell, Tongbi Jiang
  • Publication number: 20060030078
    Abstract: A substrate including a plurality of integrated circuitry die is fabricated or otherwise provided. The individual die have bond pads. A passivation layer comprising a silicone material is formed over the bond pads. Openings are formed through the silicone material to the bond pads. After the openings are formed, the die are singulated from the substrate. In one implementation, a method of fabricating integrated circuitry includes providing a substrate comprising a plurality of integrated circuitry die. Individual of the die have bond pads. A first blanket passivation layer is formed over the substrate in contact with the bond pads. A different second blanket passivation layer comprising silicone material is formed over the first passivation layer. Openings are formed through the first and second passivation layers to the bond pads. After the openings are formed, the die are singulated from the substrate. Other aspects and implementations are contemplated.
    Type: Application
    Filed: October 7, 2005
    Publication date: February 9, 2006
    Inventors: Tongbi Jiang, Mike Connell
  • Patent number: 6995041
    Abstract: A semiconductor package includes a substrate, a die attached and wire bonded to the substrate, and a die encapsulant encapsulating the die. The die includes a circuit side having a pattern of die contacts, planarized wire bonding contacts bonded to the die contacts, and a planarized polymer layer on the circuit side configured as stress defect barrier. A method for fabricating the package includes the steps of forming bumps on the die, encapsulating the bumps in a polymer layer, and then planarizing the polymer layer and the bumps to form the planarized wire bonding contacts. The method also includes the steps of attaching and wire bonding the die to the substrate, and then forming the die encapsulant on the die.
    Type: Grant
    Filed: April 30, 2003
    Date of Patent: February 7, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Mike Connell, Tongbi Jiang
  • Patent number: 6949834
    Abstract: A semiconductor package includes a substrate, a die attached and wire bonded to the substrate, and a die encapsulant encapsulating the die. The die includes a circuit side having a pattern of die contacts, planarized wire bonding contacts bonded to the die contacts, and a planarized polymer layer on the circuit side configured as stress defect barrier. A method for fabricating the package includes the steps of forming bumps on the die, encapsulating the bumps in a polymer layer, and then planarizing the polymer layer and the bumps to form the planarized wire bonding contacts. The method also includes the steps of attaching and wire bonding the die to the substrate, and then forming the die encapsulant on the die.
    Type: Grant
    Filed: March 4, 2004
    Date of Patent: September 27, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Mike Connell, Tongbi Jiang
  • Publication number: 20050158910
    Abstract: The present invention provides a semiconductor device having a protective layer for use in packaging the semiconductor device. The apparatus includes a dielectric layer, a first passivation layer formed above the dielectric layer, and a protective layer formed above the first passivation layer, the protective layer adapted to reduce stress defect failures in the semiconductor device when packaged.
    Type: Application
    Filed: March 15, 2005
    Publication date: July 21, 2005
    Inventors: Tongbi Jiang, Zhiping Yin, Mike Connell
  • Patent number: 6881606
    Abstract: The present invention provides a semiconductor device having a protective layer for use in packaging the semiconductor device. The apparatus includes a dielectric layer, a first passivation layer formed above the dielectric layer, and a protective layer formed above the first passivation layer, the protective layer adapted to reduce stress defect failures in the semiconductor device when packaged.
    Type: Grant
    Filed: March 18, 2003
    Date of Patent: April 19, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Tongbi Jiang, Zhiping Yin, Mike Connell
  • Patent number: 6812064
    Abstract: Methods are provided to improve the adhesive bonding of a semiconductor die to a substrate through an adhesive paste by forming a layer of silicon dioxide on the back surface of the semiconductor die prior to applying the adhesive paste. Contacting the semiconductor die with ozone, in a gas mixture or in a mixture with water provides rapid oxidation of the silicon layer at the back of the semiconductor die to a silicon dioxide layer of at least 10 angstroms thick, which is sufficient to greatly improve bonding to the adhesive. The formation of a silicon dioxide surface layer prior to application of the adhesive is particularly beneficial when combined with rapid, snap curing processes, where the adhesive can be reliably cured by heating the semiconductor die for less than about 1 minute.
    Type: Grant
    Filed: November 7, 2001
    Date of Patent: November 2, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Tongbi Jiang, Mike Connell, Li Li, Curtis Hollingshead
  • Publication number: 20040183163
    Abstract: The present invention provides a semiconductor device having a protective layer for use in packaging the semiconductor device. The apparatus includes a dielectric layer, a first passivation layer formed above the dielectric layer, and a protective layer formed above the first passivation layer, the protective layer adapted to reduce stress defect failures in the semiconductor device when packaged.
    Type: Application
    Filed: March 18, 2003
    Publication date: September 23, 2004
    Inventors: Tongbi Jiang, Zhiping Yin, Mike Connell
  • Patent number: 6791168
    Abstract: A semiconductor package includes a substrate, a die attached and wire bonded to the substrate, and a die encapsulant encapsulating the die. The die includes a circuit side having a pattern of die contacts, planarized wire bonding contacts bonded to the die contacts, and a planarized polymer layer on the circuit side configured as stress defect barrier. A method for fabricating the package includes the steps of forming bumps on the die, encapsulating the bumps in a polymer layer, and then planarizing the polymer layer and the bumps to form the planarized wire bonding contacts. The method also includes the steps of attaching and wire bonding the die to the substrate, and then forming the die encapsulant on the die.
    Type: Grant
    Filed: July 10, 2002
    Date of Patent: September 14, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Mike Connell, Tongbi Jiang
  • Publication number: 20040171191
    Abstract: A semiconductor package includes a substrate, a die attached and wire bonded to the substrate, and a die encapsulant encapsulating the die. The die includes a circuit side having a pattern of die contacts, planarized wire bonding contacts bonded to the die contacts, and a planarized polymer layer on the circuit side configured as stress defect barrier. A method for fabricating the package includes the steps of forming bumps on the die, encapsulating the bumps in a polymer layer, and then planarizing the polymer layer and the bumps to form the planarized wire bonding contacts. The method also includes the steps of attaching and wire bonding the die to the substrate, and then forming the die encapsulant on the die.
    Type: Application
    Filed: March 4, 2004
    Publication date: September 2, 2004
    Inventors: Mike Connell, Tongbi Jiang
  • Publication number: 20040102022
    Abstract: A substrate including a plurality of integrated circuitry die is fabricated or otherwise provided. The individual die have bond pads. A passivation layer comprising a silicone material is formed over the bond pads. Openings are formed through the silicone material to the bond pads. After the openings are formed, the die are singulated from the substrate. In one implementation, a method of fabricating integrated circuitry includes providing a substrate comprising a plurality of integrated circuitry die. Individual of the die have bond pads. A first blanket passivation layer is formed over the substrate in contact with the bond pads. A different second blanket passivation layer comprising silicone material is formed over the first passivation layer. Openings are formed through the first and second passivation layers to the bond pads. After the openings are formed, the die are singulated from the substrate. Other aspects and implementations are contemplated.
    Type: Application
    Filed: November 22, 2002
    Publication date: May 27, 2004
    Inventors: Tongbi Jiang, Mike Connell