Patents by Inventor Mike Liang

Mike Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Flip chip bump distribution on die
    Patent number: 5952726
    Abstract: An arrangement of bump pads for use on a face of a flip-chip semiconductor die. The arrangement comprises four corner regions, each corner region comprising multiple I/O bump pads and power bump pads. The corner regions are specialized bump arrangements depending upon the size of the die, signal to power ratios, and the core power requirements. The die arrangement also comprises multiple edge regions having multiple I/O bump pads and power bump pads. The edge regions are located along the edges of the die and are interleaved between the corner regions. The dimensions of the corner regions and the edge regions depend upon the power to signal ratio of the region. Also provided is a core power region having multiple power bump pads, centrally located within the edge regions and the corner groups. Core requirements mandating an odd number of rows and columns of bumps for the core require a special "checkerboard" arrangement also provided. Connections between the bumps and the edge of the die surface are shown.
    Type: Grant
    Filed: November 12, 1996
    Date of Patent: September 14, 1999
    Assignee: LSI Logic Corporation
    Inventor: Mike Liang
  • Method for distributing connection pads on a semiconductor die
    Patent number: 5885855
    Abstract: An arrangement of bump pads for use on a face of a flip-chip semiconductor die. The arrangement comprises four corner regions, each corner region comprising multiple I/O bump pads and power bump pads. The corner regions are specialized bump arrangements depending upon the size of the die, signal to power ratios, and the core power requirements. The die arrangement also comprises multiple edge regions having multiple I/O bump pads and power bump pads. The edge regions are located along the edges of the die and are interleaved between the corner regions. The dimensions of the corner regions and the edge regions depend upon the power to signal ratio of the region. Also provided is a core power region having multiple power bump pads, centrally located within the edge regions and the corner groups. Core requirements mandating an odd number of rows and columns of bumps for the core require a special "checkerboard" arrangement also provided. Connections between the bumps and the edge of the die surface are shown.
    Type: Grant
    Filed: August 14, 1997
    Date of Patent: March 23, 1999
    Assignee: LSI Logic Corporation
    Inventor: Mike Liang