Abstract: The present disclosure includes methods and apparatuses that include resistive memory. A number of embodiments include a first memory cell coupled to a data line and including a first resistive storage element and a first access device, a second memory cell coupled to the data line and including a second resistive storage element and a second access device, an isolation device formed between the first access device and the second access device, a first select line coupled to the first resistive storage element, and a second select line coupled to the second resistive storage element, wherein the second select line is separate from the first select line.

Abstract: The present disclosure includes methods and apparatuses that include resistive memory. A number of embodiments include a first memory cell coupled to a data line and including a first resistive storage element and a first access device, a second memory cell coupled to the data line and including a second resistive storage element and a second access device, an isolation device formed between the first access device and the second access device, a first select line coupled to the first resistive storage element, and a second select line coupled to the second resistive storage element, wherein the second select line is separate from the first select line.

Abstract: The present disclosure includes methods and apparatuses that include resistive memory. A number of embodiments include a first memory cell coupled to a data line and including a first resistive storage element and a first access device, a second memory cell coupled to the data line and including a second resistive storage element and a second access device, an isolation device formed between the first access device and the second access device, a first select line coupled to the first resistive storage element, and a second select line coupled to the second resistive storage element, wherein the second select line is separate from the first select line.

Abstract: A resistive memory structure, for example, phase change memory structure, includes one access device and two or more resistive memory cells. Each memory cell is coupled to a rectifying device to prevent parallel leak current from flowing through non-selected memory cells. In an array of resistive memory bit structures, resistive memory cells from different memory bit structures are stacked and share rectifying devices.

Abstract: A phase change memory cell and methods of fabricating the same are presented. The memory cell includes a variable resistance region and a top and bottom electrode. The shapes of the variable resistance region and the top electrode are configured to evenly distribute a current with a generally hemispherical current density distribution around the first electrode.

Abstract: The present disclosure includes methods and apparatuses that include resistive memory. A number of embodiments include a first memory cell coupled to a data line and including a first resistive storage element and a first access device, a second memory cell coupled to the data line and including a second resistive storage element and a second access device, an isolation device formed between the first access device and the second access device, a first select line coupled to the first resistive storage element, and a second select line coupled to the second resistive storage element, wherein the second select line is separate from the first select line.

Abstract: Methods and apparatuses that include resistive memory can include a first memory cell coupled to a data line and including a first resistive storage element and a first access device, a second memory cell coupled to the data line and including a second resistive storage element and a second access device, an isolation device formed between the first access device and the second access device, a first select line coupled to the first resistive storage element, and a second select line coupled to the second resistive storage element, wherein the second select line is separate from the first select line.

Abstract: A phase change memory element and method of forming the same. The memory element includes a phase change material layer electrically coupled to first and second conductive material layers. A energy conversion layer is formed in association with the phase change material layer, and electrically coupled to a third conductive material layer. An electrically isolating material layer is formed between the phase change material layer and the energy conversion layer.

Abstract: A memory element and method of forming the same. The memory element includes a substrate supporting a first electrode, a dielectric layer over the first electrode having a via exposing a portion of the first electrode, a phase change material layer formed over sidewalls of the via and contacting the exposed portion of the first electrode, insulating material formed over the phase change material layer and a second electrode formed over the insulating material and contacting the phase change material layer.

Abstract: The present disclosure includes methods and apparatuses that include resistive memory. A number of embodiments include a first memory cell coupled to a data line and including a first resistive storage element and a first access device, a second memory cell coupled to the data line and including a second resistive storage element and a second access device, an isolation device formed between the first access device and the second access device, a first select line coupled to the first resistive storage element, and a second select line coupled to the second resistive storage element, wherein the second select line is separate from the first select line.

Abstract: A phase change memory element and method of forming the same. The memory element includes a phase change material layer electrically coupled to first and second conductive material layers. A energy conversion layer is formed in association with the phase change material layer, and electrically coupled to a third conductive material layer. An electrically isolating material layer is formed between the phase change material layer and the energy conversion layer.

Abstract: A phase change memory cell and methods of fabricating the same are presented. The memory cell includes a variable resistance region and a top and bottom electrode. The shapes of the variable resistance region and the top electrode are configured to evenly distribute a current with a generally hemispherical current density distribution around the first electrode.

Abstract: A phase change memory element and method of forming the same. The memory element includes a phase change material layer electrically coupled to first and second conductive material layers. A energy conversion layer is formed in association with the phase change material layer, and electrically coupled to a third conductive material layer. An electrically isolating material layer is formed between the phase change material layer and the energy conversion layer.

Abstract: A phase change memory cell and methods of fabricating the same are presented. The memory cell includes a variable resistance region and a top and bottom electrode. The shapes of the variable resistance region and the top electrode are configured to evenly distribute a current with a generally hemispherical current density distribution around the first electrode.

Abstract: A data storage device and methods for storing and reading data are provided. The data storage device includes a data storage medium and second device. The data storage medium has an insulating layer, a first electrode layer over the insulating layer and at least one layer of resistance variable material over the first electrode layer. The second device includes a substrate and at least one conductive point configured to electrically contact the data storage medium.

Abstract: A resistive memory structure, for example, phase change memory structure, includes one access device and two or more resistive memory cells. Each memory cell is coupled to a rectifying device to prevent parallel leak current from flowing through non-selected memory cells. In an array of resistive memory bit structures, resistive memory cells from different memory bit structures are stacked and share rectifying devices.

Abstract: A resistive memory structure, for example, phase change memory structure, includes one access device and two or more resistive memory cells. Each memory cell is coupled to a rectifying device to prevent parallel leak current from flowing through non-selected memory cells. In an array of resistive memory bit structures, resistive memory cells from different memory bit structures are stacked and share rectifying devices.

Abstract: A data storage device and methods for storing and reading data are provided. The data storage device includes a data storage medium and second device. The data storage medium has an insulating layer, a first electrode layer over the insulating layer and at least one layer of resistance variable material over the first electrode layer. The second device includes a substrate and at least one conductive point configured to electrically contact the data storage medium.

Abstract: A phase change memory structure with multiple resistance states and methods of forming, programming, and sensing the same. The memory structure includes two or more phrase change elements provided between electrodes. Each phase change element has a respective resistance curve as a function of programming voltage which is shifted relative to the resistance curves of other phase change elements. In one example structure using two phase change elements, the memory structure is capable of switching among four resistance states.

Abstract: A phase change memory structure with multiple resistance states and methods of forming, programming, and sensing the same. The memory structure includes two or more phrase change elements provided between electrodes. Each phase change element has a respective resistance curve as a function of programming voltage which is shifted relative to the resistance curves of other phase change elements. In one example structure using two phase change elements, the memory structure is capable of switching among four resistance states.