Patents by Inventor Mikihiko Ito

Mikihiko Ito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11270981
    Abstract: According to one embodiment, a memory device includes: a first chip including a first circuit, first and second terminals; a second chip including a second circuit and a third terminal; and an interface chip including first and second voltage generators. The first chip is between the second chip and the interface chip. The first terminal is connected between the first circuit and the first voltage generator. A third end of the second terminal is connected to the third terminal and a fourth end of the second terminal is connected to the second voltage generator. A fifth end of the third terminal is connected to the second circuit and a sixth end of the third terminal is connected to the second voltage generator via the second terminal. The third end overlaps with the sixth end, without overlapping with the fourth end.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: March 8, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Mikihiko Ito, Masaru Koyanagi, Masafumi Nakatani, Shinya Okuno, Shigeki Nagasaka, Masahiro Yoshihara, Akira Umezawa, Satoshi Tsukiyama, Kazushige Kawasaki
  • Patent number: 11211130
    Abstract: A semiconductor device comprises an input circuit that includes a first comparator configured to output a first output signal and a second output signal having a phase opposite to that of the first output signal, based on a comparison result of a first input signal and a second input signal which is a complementary signal of the first input signal. A duty ratio of the first output signal and a duty ratio of the second output signal are different from a duty ratio of the first input signal and a duty ratio of the second input signal, respectively.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: December 28, 2021
    Assignee: KIOXIA CORPORATION
    Inventors: Yasuhiro Hirashima, Masaru Koyanagi, Mikihiko Ito, Kei Shiraishi, Fumiya Watanabe
  • Publication number: 20210295930
    Abstract: According to one embodiment, in a semiconductor integrated circuit, an input circuit has an input and an output stage electrically connected to the input stage via a first node and a second node. The input stage includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first time constant adjusting circuit and a second time constant adjusting circuit. The first transistor has a gate that receives an input signal. The second transistor has a gate that receives a reference signal. The third transistor is disposed adjacent to a drain of the first transistor. The fourth transistor is disposed adjacent to a drain of the second transistor. The first time constant adjusting circuit is electrically connected between a gate of the third transistor and the first node. The second time constant adjusting circuit is electrically connected between a gate of the fourth transistor and the second node.
    Type: Application
    Filed: December 11, 2020
    Publication date: September 23, 2021
    Applicant: Kioxia Corporation
    Inventors: Fumiya WATANABE, Masaru KOYANAGI, Yutaka SHIMIZU, Yasuhiro HIRASHIMA, Kei SHIRAISHI, Mikihiko ITO
  • Publication number: 20210005580
    Abstract: According to one embodiment, a memory device includes: a first chip including a first circuit, first and second terminals; a second chip including a second circuit and a third terminal; and an interface chip including first and second voltage generators. The first chip is between the second chip and the interface chip. The first terminal is connected between the first circuit and the first voltage generator. A third end of the second terminal is connected to the third terminal and a fourth end of the second terminal is connected to the second voltage generator. A fifth end of the third terminal is connected to the second circuit and a sixth end of the third terminal is connected to the second voltage generator via the second terminal. The third end overlaps with the sixth end, without overlapping with the fourth end.
    Type: Application
    Filed: September 17, 2020
    Publication date: January 7, 2021
    Applicant: Toshiba Memory Corporation
    Inventors: Mikihiko ITO, Masaru KOYANAGI, Masafumi NAKATANI, Shinya OKUNO, Shigeki NAGASAKA, Masahiro YOSHIHARA, Akira UMEZAWA, Satoshi TSUKIYAMA, Kazushige KAWASAKI
  • Patent number: 10847232
    Abstract: A semiconductor memory device includes a differential waveform shaping circuit including first and waveform shaping circuits connected in parallel. The first waveform shaping circuit has a first inverting amplifier, and two inverters connected in series. The first inverting amplifier inverts and differentially amplifies an input signal having a rectangular waveform. Then, the output of the first inverting amplifier is passed through the two inverters. The second waveform shaping circuit has a first inverter, a second inverting amplifier, and a second inverter connected in series. The second inverting amplifier inverts and differentially amplifies the output signal from the first invertor, and the second inverter inverts the output signal from the second inverting amplifier. The differential waveform shaping circuit generates an output signal by averaging the output signal from the first waveform shaping circuit and the output signal from the second waveform shaping circuit.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: November 24, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kei Shiraishi, Masaru Koyanagi, Mikihiko Ito, Yumi Takada, Yasuhiro Hirashima, Satoshi Inoue, Kensuke Yamamoto, Shouichi Ozaki, Taichi Wakui, Fumiya Watanabe
  • Patent number: 10811393
    Abstract: According to one embodiment, a memory device includes: a first chip including a first circuit, first and second terminals; a second chip including a second circuit and a third terminal; and an interface chip including first and second voltage generators. The first chip is between the second chip and the interface chip. The first terminal is connected between the first circuit and the first voltage generator. A third end of the second terminal is connected to the third terminal and a fourth end of the second terminal is connected to the second voltage generator. A fifth end of the third terminal is connected to the second circuit and a sixth end of the third terminal is connected to the second voltage generator via the second terminal. The third end overlaps with the sixth end, without overlapping with the fourth end.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: October 20, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Mikihiko Ito, Masaru Koyanagi, Masafumi Nakatani, Shinya Okuno, Shigeki Nagasaka, Masahiro Yoshihara, Akira Umezawa, Satoshi Tsukiyama, Kazushige Kawasaki
  • Patent number: 10790266
    Abstract: According to one embodiment, a memory device includes: a first chip including a first circuit, first and second terminal; a second chip including a second circuit and a third terminal; and an interface chip including first and second voltage generators. The first chip is between the second chip and the interface chip. The first terminal is connected between the first circuit and the first voltage generator. A third end of the second terminal is connected to the third terminal and a fourth end of the second terminal is connected to the second voltage generator. A fifth end of the third terminal is connected to the second circuit and a sixth end of the third terminal is connected to the second voltage generator via the second terminal. The third end overlaps with the sixth end, without overlapping with the fourth end.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: September 29, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Mikihiko Ito, Masaru Koyanagi, Masafumi Nakatani, Masahiro Yoshihara, Shinya Okuno, Shigeki Nagasaka
  • Publication number: 20200265902
    Abstract: A semiconductor device comprises an input circuit that includes a first comparator configured to output a first output signal and a second output signal having a phase opposite to that of the first output signal, based on a comparison result of a first input signal and a second input signal which is a complementary signal of the first input signal. A duty ratio of the first output signal and a duty ratio of the second output signal are different from a duty ratio of the first input signal and a duty ratio of the second input signal, respectively.
    Type: Application
    Filed: May 5, 2020
    Publication date: August 20, 2020
    Inventors: Yasuhiro HIRASHIMA, Masaru KOYANAGI, Mikihiko ITO, Kei SHIRAISHI, Fumiya WATANABE
  • Patent number: 10734360
    Abstract: A semiconductor device includes a base member and semiconductor chips stacked on the base member. The semiconductor chips include a first semiconductor chip and a second semiconductor chip adjacent to the first semiconductor chip. The first semiconductor chip includes a semiconductor substrate, a functional layer and through electrodes. The through electrodes extend from the back surface to the front surface of the semiconductor substrate, and are electrically connected to the functional layer on the front surface. The second semiconductor chip is electrically connected to the first semiconductor chip through connection members connected to the through electrodes. The functional layer includes first and second contact pads. The second contact pad is positioned at a level between the semiconductor substrate and the first contact pad. The through electrodes include a first through electrode connected to the first contact pad and a second through electrode connected to the second contact pad.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: August 4, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Satoshi Tsukiyama, Masaru Koyanagi, Mikihiko Ito, Kazushige Kawasaki
  • Publication number: 20200202959
    Abstract: A semiconductor memory device includes a differential waveform shaping circuit including first and waveform shaping circuits connected in parallel. The first waveform shaping circuit has a first inverting amplifier, and two inverters connected in series. The first inverting amplifier inverts and differentially amplifies an input signal having a rectangular waveform. Then, the output of the first inverting amplifier is passed through the two inverters. The second waveform shaping circuit has a first inverter, a second inverting amplifier, and a second inverter connected in series. The second inverting amplifier inverts and differentially amplifies the output signal from the first invertor, and the second inverter inverts the output signal from the second inverting amplifier. The differential waveform shaping circuit generates an output signal by averaging the output signal from the first waveform shaping circuit and the output signal from the second waveform shaping circuit.
    Type: Application
    Filed: August 29, 2019
    Publication date: June 25, 2020
    Inventors: Kei SHIRAISHI, Masaru KOYANAGI, Mikihiko ITO, Yumi TAKADA, Yasuhiro HIRASHIMA, Satoshi INOUE, Kensuke YAMAMOTO, Shouichi OZAKI, Taichi WAKUI, Fumiya WATANABE
  • Patent number: 10679710
    Abstract: A semiconductor device comprises an input circuit that includes a first comparator configured to output a first output signal and a second output signal having a phase opposite to that of the first output signal, based on a comparison result of a first input signal and a second input signal which is a complementary signal of the first input signal. A duty ratio of the first output signal and a duty ratio of the second output signal are different from a duty ratio of the first input signal and a duty ratio of the second input signal, respectively.
    Type: Grant
    Filed: September 2, 2018
    Date of Patent: June 9, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yasuhiro Hirashima, Masaru Koyanagi, Mikihiko Ito, Kei Shiraishi, Fumiya Watanabe
  • Patent number: 10593649
    Abstract: A semiconductor device includes a base member, a stacked body on the base member, a first conductor on the stacked body, a second conductor on a top surface of the base member, and a connection conductor connecting the first conductor and the second conductor. The stacked body includes semiconductor chips stacked and a shared terminal connected to the plurality of semiconductor chips. The plurality of semiconductor chips each includes a functional element on a front surface side thereof and a through electrode extending from a back surface to the front surface side. The shared terminal has a top end positioned at a top surface of the stacked body and a bottom end positioned at a bottom surface of the stacked body. The first conductor is connected to the top end of the shared terminal, and the second conductor is electrically connected to the bottom end of the shared terminal.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: March 17, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Satoshi Tsukiyama, Masaru Koyanagi, Mikihiko Ito, Kazushige Kawasaki
  • Patent number: 10482977
    Abstract: A semiconductor memory device includes a first transistor including a first end connected to a first pad and a second end connected to a first node, a second transistor including a first end connected to a second pad and a second end connected to the first node, a third transistor including a first end connected to the second pad, a second end connected to the first node, and a gate connected to a second node and having a size different from that of the second transistor, a fourth transistor including a first end connected to the first pad, a second end connected to the second node, and a gate connected to the first node, and a fifth transistor including a first end connected to the second pad, a second end connected to the second node, and a gate connected to the first node.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: November 19, 2019
    Assignee: TOSHIBA MEMEORY CORPORATION
    Inventors: Kei Shiraishi, Masaru Koyanagi, Mikihiko Ito, Yasuhiro Hirashima
  • Patent number: 10452588
    Abstract: A semiconductor device includes first input/output circuits for a first channel, first input/output pads corresponding to the first input/output circuits, respectively, wherein the first input/output pads are aligned along and extends in a first direction, second input/output circuits for the first channel, second input/output pads corresponding to the second input/output circuits, respectively, wherein the second input/output pads are aligned along and extends in a second direction, and an input circuit between the first input/output pads and the second input/output pads, and connected to a memory to which the input circuit inputs data from the first input/output circuits and the second input/output circuits. The input circuit is positioned such that a first line extending perpendicular to the first direction from one of the first input/output pads and a second line extending perpendicular to the second direction from one of the second input/output pads intersect a portion of the input circuit.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: October 22, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Mikihiko Ito, Masaru Koyanagi
  • Publication number: 20190295987
    Abstract: A semiconductor device includes a base member, a stacked body on the base member, a first conductor on the stacked body, a second conductor on a top surface of the base member, and a connection conductor connecting the first conductor and the second conductor. The stacked body includes semiconductor chips stacked and a shared terminal connected to the plurality of semiconductor chips. The plurality of semiconductor chips each includes a functional element on a front surface side thereof and a through electrode extending from a back surface to the front surface side. The shared terminal has a top end positioned at a top surface of the stacked body and a bottom end positioned at a bottom surface of the stacked body. The first conductor is connected to the top end of the shared terminal, and the second conductor is electrically connected to the bottom end of the shared terminal.
    Type: Application
    Filed: September 4, 2018
    Publication date: September 26, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Satoshi Tsukiyama, Masaru Koyanagi, Mikihiko Ito, Kazushige Kawasaki
  • Publication number: 20190295661
    Abstract: A semiconductor device comprises an input circuit that includes a first comparator configured to output a first output signal and a second output signal having a phase opposite to that of the first output signal, based on a comparison result of a first input signal and a second input signal which is a complementary signal of the first input signal. A duty ratio of the first output signal and a duty ratio of the second output signal are different from a duty ratio of the first input signal and a duty ratio of the second input signal, respectively.
    Type: Application
    Filed: September 2, 2018
    Publication date: September 26, 2019
    Inventors: Yasuhiro HIRASHIMA, Masaru KOYANAGI, Mikihiko ITO, Kei SHIRAISHI, Fumiya WATANABE
  • Publication number: 20190295988
    Abstract: A semiconductor device includes a base member and semiconductor chips stacked on the base member. The semiconductor chips include a first semiconductor chip and a second semiconductor chip adjacent to the first semiconductor chip. The first semiconductor chip includes a semiconductor substrate, a functional layer and through electrodes. The through electrodes extend from the back surface to the front surface of the semiconductor substrate, and are electrically connected to the functional layer on the front surface. The second semiconductor chip is electrically connected to the first semiconductor chip through connection members connected to the through electrodes. The functional layer includes first and second contact pads. The second contact pad is positioned at a level between the semiconductor substrate and the first contact pad. The through electrodes include a first through electrode connected to the first contact pad and a second through electrode connected to the second contact pad.
    Type: Application
    Filed: September 4, 2018
    Publication date: September 26, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Satoshi TSUKIYAMA, Masaru KOYANAGI, Mikihiko ITO, Kazushige KAWASAKI
  • Patent number: 10359961
    Abstract: According to one embodiment, there is provided a storage device including a control chip and a plurality of memory chips. The control chip has an input buffer common to the control chip and the plurality of memory chips and electrically connected to an external terminal. A first transmission path going through the input buffer and a second transmission path not going through the input buffer are provided between the external terminal and the plurality of memory chips. In a first mode, the control chip enables the input buffer so as to activate the first transmission path and, in a second mode, disables the input buffer so as to activate the second transmission path.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: July 23, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Mikihiko Ito, Masaru Koyanagi, Shintaro Hayashi
  • Publication number: 20190206495
    Abstract: According to one embodiment, a memory device includes: a first chip including a first circuit, first and second terminal; a second chip including a second circuit and a third terminal; and an interface chip including first and second voltage generators. The first chip is between the second chip and the interface chip. The first terminal is connected between the first circuit and the first voltage generator. A third end of the second terminal is connected to the third terminal and a fourth end of the second terminal is connected to the second voltage generator. A fifth end of the third terminal is connected to the second circuit and a sixth end of the third terminal is connected to the second voltage generator via the second terminal. The third end overlaps with the sixth end, without overlapping with the fourth end.
    Type: Application
    Filed: March 11, 2019
    Publication date: July 4, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Mikihiko ITO, Masaru KOYANAGI, Masafumi NAKATANI, Masahiro YOSHIHARA, Shinya OKUNO, Shigeki NAGASAKA
  • Publication number: 20190206845
    Abstract: According to one embodiment, a memory device includes: a first chip including a first circuit, first and second terminals; a second chip including a second circuit and a third terminal; and an interface chip including first and second voltage generators. The first chip is between the second chip and the interface chip. The first terminal is connected between the first circuit and the first voltage generator. A third end of the second terminal is connected to the third terminal and a fourth end of the second terminal is connected to the second voltage generator. A fifth end of the third terminal is connected to the second circuit and a sixth end of the third terminal is connected to the second voltage generator via the second terminal. The third end overlaps with the sixth end, without overlapping with the fourth end.
    Type: Application
    Filed: March 11, 2019
    Publication date: July 4, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Mikihiko ITO, Masaru Koyanagi, Masafumi Nakatani, Shinya Okuno, Shigeki Nagasaka, Masahiro Yoshihara, Akira Umezawa, Satoshi Tsukiyama, Kazushige Kawasaki