Abstract: According to one embodiment, a system includes a central control device connected to a plurality of sub-devices each having an embedded computer. The central control device is configured to detect an anomality caused by a cyberattack, transmit a stop instruction to each of the sub-devices to stop an operation of the system, transmit a restart instruction to each of the sub-devices to restart each of the sub-devices by secure boot, transmit a diagnostic instruction to at least one sub-device to diagnose whether or not physical elements configuring the system are degraded and determine whether or not to resume the operation of the system based on a result of the restart executed in each of the sub-devices and a result of the diagnosis executed in the at least one sub-device.

Abstract: According to one embodiment, a data protection apparatus includes a processor configured to execute an encryption process on log data including a data frame including a plurality of pieces of data generated along a time sequence. The processor is configured to encrypt each of the pieces of data with a corresponding encryption key among a first initial key and a first encryption keys generated in a forward direction to a time sequence of the pieces of data. The processor is configured to encrypt each of a plurality of pieces of data encrypted with the corresponding encryption key with a corresponding encryption key among a second initial key and a second encryption keys generated in a backward direction to a time sequence of the pieces of data.

Abstract: An electronic apparatus includes a controller. The controller includes an instruction executer configured to generate or acquire data, an issuer configured to accept a request and issues a time stamp, a first updater configured to update a first counter value according to a first operation, a second updater configured to update a second counter value in accordance with issuance of the time stamp, a first non-volatile memory to hold the first counter value and a secret key, and a volatile register to hold the second counter value. The time stamp is a message authentication code or a digital signature issued from the first and second counter values and the data. The second counter value is not stored in the first non-volatile memory.

Abstract: According to one embodiment, an information processing apparatus is allowed to access a storage device storing time-series data generated by a first device. The information processing apparatus includes a processor holding a first public key and a first private key. The processor is configured to acquire a program for correcting an error in first data on a first product from a first entity. The processor is configured to correct the correction target first data, using data in a predetermined range of the time-series data. The processor is configured to generate ground data indicating correction grounds for the corrected correction target first data, based on the data in the predetermined range, and add the ground data to the corrected correction target first data.

Abstract: According to one embodiment, an information processing apparatus is allowed to access a storage device storing time-series data generated by a first device. The information processing apparatus includes a processor holding a first public key and a first private key. The processor is configured to acquire a program for correcting an error in first data on a first product from a first entity. The processor is configured to correct the correction target first data, using data in a predetermined range of the time-series data. The processor is configured to generate ground data indicating correction grounds for the corrected correction target first data, based on the data in the predetermined range, and add the ground data to the corrected correction target first data.

Abstract: An electronic apparatus includes: a processor configured to execute a firmware program and a monitor program exclusively, switch between multiple operation modes, and start up the firmware program according to the monitor program; and nonvolatile memory which includes, storage regions for a plurality of firmware programs, a signature table that holds signatures of the firmware programs individually stored in the storage regions or a signature of a firmware program including an identification number of an update notification used for update, a firmware program storage for information specifying a firmware program selected to be executed, a first storage that holds an execution result of a firmware program selected in accordance with the monitor program, a second storage that holds the update notification acquired by the execution of the firmware program, and a third storage that holds a maximum identification number of firmware programs that have been executed.

Abstract: According to one embodiment, a data protection apparatus includes a processor configured to execute an encryption process on log data including a data frame including a plurality of pieces of data generated along a time sequence. The processor is configured to encrypt each of the pieces of data with a corresponding encryption key among a first initial key and a first encryption keys generated in a forward direction to a time sequence of the pieces of data. The processor is configured to encrypt each of a plurality of pieces of data encrypted with the corresponding encryption key with a corresponding encryption key among a second initial key and a second encryption keys generated in a backward direction to a time sequence of the pieces of data.

Abstract: A control device of the present embodiment has a communication I/F, a built-in non-volatile memory, a controller, an external-serial-memory I/F, a security management module, and an access controller. The communication I/F enables communication with outside. The built-in non-volatile memory has a first storage region, which stores an initialization program which carries out initialization operation, and a second storage region, which stores currently used firmware which is executed after the initialization operation and acquires firmware for update via the communication I/F. The controller executes the initialization program and the currently used firmware. The external-serial-memory I/F communicably connects the device of its own to an external non-volatile memory via a serial bus. The security-mode management module fixes an access control setting of the built-in non-volatile memory and the external non-volatile memory. The access controller outputs a level signal different from the serial bus.

Abstract: According to one embodiment, an information processing device includes a processor, a controller, and a memory. The memory stores a vector address related to an interrupt request executed on condition that the processor is in a sleep state. The controller receives the interrupt request and detects that the processor transitions to the sleep state, detects fetch of the vector address of the interrupt request after the sleep state of the processor is detected, and inputs the vector address that is related to the interrupt request and stored in the memory into the processor in a case where the fetch of the vector address of the interrupt request is detected.

Abstract: An information processing device updates its own secret key according to an update request including request order information, the information processing device being provided with: a storage unit that stores, in a nonvolatile manner, a master secret key, a secret key, and order comparison information that enables comparison of the request order of the update request; and an update unit that, in a case where the update request has been made, compares the request order information and the order comparison information, and in a case where it has been determined that the order of the update request is authorized, updates the order comparison information to information corresponding to the request order information before update processing of the secret key is performed by using the master secret key.

Abstract: A control device of the present embodiment has a communication I/F, a built-in non-volatile memory, a controller, an external-serial-memory I/F, a security management module, and an access controller. The communication I/F enables communication with outside. The built-in non-volatile memory has a first storage region, which stores an initialization program which carries out initialization operation, and a second storage region, which stores currently used firmware which is executed after the initialization operation and acquires firmware for update via the communication I/F. The controller executes the initialization program and the currently used firmware. The external-serial-memory I/F communicably connects the device of its own to an external non-volatile memory via a serial bus. The security-mode management module fixes an access control setting of the built-in non-volatile memory and the external non-volatile memory. The access controller outputs a level signal different from the serial bus.

Abstract: According to one embodiment, an information processing apparatus is applied to an embedded system in an electric device and includes a first circuit. The first circuit is configured to request a server different from the information processing apparatus to determine whether a debug or software change is possible in response to external access.

Abstract: According to one embodiment, an electronic apparatus includes a controller. The control unit includes an instruction executer configured to generate or acquire data, an issuer configured to accept a request and issues a time stamp, a first updater configured to update a first counter value according to a first operation, a second updater configured to update a second counter value in accordance with issuance of the time stamp, a first non-volatile memory to hold the first counter value and a secret key, and a volatile register to hold the second counter value. The time stamp is a message authentication code or a digital signature issued from the first and second counter values and the data. The second counter value is not stored in the first non-volatile memory.

Abstract: An electronic apparatus includes: a processor configured to execute a firmware program and a monitor program exclusively, switch between multiple operation modes, and start up the firmware program according to the monitor program; and nonvolatile memory which includes, storage regions for a plurality of firmware programs, a signature table that holds signatures of the firmware programs individually stored in the storage regions or a signature of a firmware program including an identification number of an update notification used for update, a firmware program storage for information specifying a firmware program selected to be executed, a first storage that holds an execution result of a firmware program selected in accordance with the monitor program, a second storage that holds the update notification acquired by the execution of the firmware program, and a third storage that holds a maximum identification number of firmware programs that have been executed.

Abstract: According to one embodiment, an information processing device includes a processor, a controller, and a memory. The memory stores a vector address related to an interrupt request executed on condition that the processor is in a sleep state. The controller receives the interrupt request and detects that the processor transitions to the sleep state, detects fetch of the vector address of the interrupt request after the sleep state of the processor is detected, and inputs the vector address that is related to the interrupt request and stored in the memory into the processor in a case where the fetch of the vector address of the interrupt request is detected.

Abstract: An information processing device according to an embodiment updates its own secret key according to an update request including request order information, the information processing device being provided with: a storage unit that stores, in a nonvolatile manner, a master secret key, a secret key, and order comparison information that enables comparison of the request order of the update request; and an update unit that, in a case where the update request has been made, compares the request order information and the order comparison information, and in a case where it has been determined that the order of the update request is authorized, updates the order comparison information to information corresponding to the request order information before update processing of the secret key is performed by using the master secret key.

Abstract: According to one embodiment, an information processing apparatus is applied to an embedded system in an electric device and includes a first circuit. The first circuit is configured to request a server different from the information processing apparatus to determine whether a debug or software change is possible in response to external access.

Abstract: An information processing apparatus includes a nonvolatile memory, a flag settable to a first value indicating that a program stored in a memory region of the nonvolatile memory has not been verified, and to a second value indicating that the program has been verified, a switching circuit configured to set the flag to the first value, in response to a request for permission to modify the program stored in the memory region, and a verification circuit that sets the flag to the second value upon verification of the program stored in the memory region, and upon restart of the information processing apparatus, carries out a verification process of the program prior to execution of the program if the first value is set in the flag, and executes the program without the verification process if the second value is set in the flag.

Abstract: An information processing apparatus according to an embodiment includes a reception unit and switching unit. The reception unit receives an interrupt. The switching unit that switches a second operating system (OS) which is executing in a core to a first OS to which the interrupt for the first OS is input, when the reception unit receives an interrupt for the core in which the first OS is a priority OS and the second OS is not the priority OS.

Abstract: According to one embodiment, an information processing device includes a processor, a nonvolatile memory, a designation unit, and a controller. The nonvolatile memory stores the first software and the second software which is used as substitute for the first software. The designation unit designates software to be executed by the processor at a boot. The controller protects an area of the nonvolatile memory storing the first software from being written while the first software is executed by the processor. When third software is executed by the processor, the third software verifies the second software. When the second software is legal in a result of verifying by the third software, the designation unit designates the second software.