Abstract: The on-chip multi-core type tamper resistant processor has a feature that, on the microprocessor package which has a plurality of instruction execution cores on an identical package and an ciphering processing function that can use a plurality of ciphering keys in correspondence to programs under a multi-task program execution environment, a key table for storing ciphering keys and the ciphering processing function are concentrated on a single location on the package, such that it is possible to provide a tamper resistant microprocessor in the multi-processor configuration that can realize the improved processing performance by hardware of a given size compared with the case of providing the key table and the ciphering processing function distributedly.

Abstract: In a tamper resistant microprocessor having a cache memory, the cache memory stores the decrypted execution code or data into one of cache lines provided in the cache memory, each cache line having a secret protection attribute holding section for storing an actual encryption key used in decrypting the execution code or data, and a cache memory control unit processes a reading request for the execution code or data such that, if the execution code or data exists in the cache memory and the execution code or data in the cache memory is decrypted by an identical encryption key as the prescribed encryption key, the execution code or data in the cache memory is read out.

Abstract: A pressure sensor package of the present invention includes a pressure sensor including a cavity disposed within a semiconductor substrate, wherein a region of the substrate above the cavity comprises a diaphragm section; a plurality of pressure-sensitive elements, wherein at least of portion of each pressure-sensitive element is disposed on the diaphragm section; and a plurality of conductive portions laterally spaced from the cavity and electrically connected to the pressure sensitive elements, a plurality of electrically conductive bumps arranged on the conductive portions and electrically connected to the conductive portions, wherein a total thickness D1 of the semiconductor substrate, a thickness D2 of the diaphragm section, a thickness D3 of the cavity, and a thickness D4=D1?(D2+D3) satisfy the relationships: (D2+D3) in a range of approximately 5-20 ?m, and D1 not less than about 100 ?m.

Abstract: A first storage unit stores a plurality of security functions each defining a first protection attribute requiring a storage of a value of an argument for input/output of data. A second storage unit stores a program list describing a second protection attribute of a variable indicating a storage area of the data and an executing procedure of a predetermined process. An identifying unit identifies a third protection attribute of an actual argument for input/output of a security function based on the second protection attribute. When a judging unit judges not all of third protection attributes match with first protection attributes, an output unit outputs error information indicating a mismatch of the protection attributes.

Abstract: A tamper resistant microprocessor has a task state table for assigning a task identifier to a task that can take a plurality of states, and storing a state of the task in correspondence to the task identifier; a task register for storing the task identifier of a currently executed task; an interface for reading a program stored in a form encrypted by using a program key at an external memory, in units of cache lines, when a request for the task is made; an encryption processing unit for generating decryption keys that are different for different cache lines, according to the program key, and decrypt a content read by the interface; a cache memory formed by a plurality of cache lines each having a tag, for storing the task identifier corresponding to a decryption key used in decrypting each cache line in the tag of each cache line; and an access check unit for comparing the task identifier stored in the tag of each cache line with a value of the task register, and discarding a content of each cache line when t

Abstract: A data transmitting node and a network inter-connection node suitable for use in the home network environment. In a case of transmitting information data from a data transmitting node connected with a physical network to a receiving node connected with the physical network or another physical network, a data transmitting node transmits the control message including an IP address information of a data transmission destination, a header/channel information dependent on the physical network, and an information indicating that the information data to be transmitted according to the header/channel information is data in an upper layer of an IP layer. The information data is then transmitted to the receiving node, where the information data contains the header/channel information and data of the upper layer without IP packet encapsulation. A network inter-connection node operates similarly.

Abstract: A pressure sensor package of the present invention includes a pressure sensor including a cavity disposed within a semiconductor substrate, wherein a region of the substrate above the cavity comprises a diaphragm section; a plurality of pressure-sensitive elements, wherein at least of portion of each pressure-sensitive element is disposed on the diaphragm section; and a plurality of conductive portions laterally spaced from the cavity and electrically connected to the pressure sensitive elements, a plurality of electrically conductive bumps arranged on the conductive portions and electrically connected to the conductive portions, wherein a total thickness D1 of the semiconductor substrate, a thickness D2 of the diaphragm section, a thickness D3 of the cavity, and a thickness D4=D1?(D2+D3) satisfy the relationships: (D2+D3) in a range of approximately 5-20 ?m, and D1 not less than about 100 ?m.

Abstract: A scheme for realizing communications through an external network such as telephone network from a contents processing device such as AV device or PC connected to a local network such as home network is disclosed. The contents processing device solicits a set up of connection to the server device through the telephone network, to a gateway device which is connected with both the home network and the telephone network. Then, the gateway device carries out a call set up with respect to a specified address on the telephone network, upon receiving the solicitation from the contents processing device, and transfers data transmitted from the contents processing device to a connection established by the call set up, and data arriving from the connection established by the call set up to the contents processing device.

Abstract: A tamper resistant microprocessor has a task state table for assigning a task identifier to a task that can take a plurality of states, and storing a state of the task in correspondence to the task identifier; a task register for storing the task identifier of a currently executed task; an interface for reading a program stored in a form encrypted by using a program key at an external memory, in units of cache lines, when a request for the task is made; an encryption processing unit for generating decryption keys that are different for different cache lines, according to the program key, and decrypt a content read by the interface; a cache memory formed by a plurality of cache lines each having a tag, for storing the task identifier corresponding to a decryption key used in decrypting each cache line in the tag of each cache line; and an access check unit for comparing the task identifier stored in the tag of each cache line with a value of the task register, and discarding a content of each cache line when t

Abstract: A data transfer control device and a relay device which are suitable for use in the home network environment. For a case of controlling transfer of information data to a receiving node connected with a first physical network from a transmitting node connected with a second physical network, there is provided a data transfer control device connected with the second physical network which has: an establishing unit for establishing a channel in the second physical network for transmitting the information data; a reserving unit for reserving a communication path for transferring the information data transmitted through that channel to another data transfer control device belonging to the first physical network and/or the receiving node; and a commanding unit for commanding the transmitting node to transmit the information data through that channel, by using a protocol depending oh the second physical network.

Abstract: Under a multi-task environment, a tamper resistant microprocessor saves a context information for one program whose execution is to be interrupted, where the context information contains information indicating an execution state of that one program and the execution code encryption key of that one program. An execution of that one program can be restarted by recovering the execution state of that one program from the saved context information. The context information can be encrypted by using the public key of the microprocessor, and then decrypted by using the secret key of the microprocessor.

Abstract: In the method for sharing encrypted data region among two or more processes on a tamper resistant processor, one process creates the encrypted data region to be shared according to the common key generated as a result of the safe key exchange, and the other process maps that region to its own address space or process space. The address information of the shared encrypted data region and the common key of each process are set in relation in the encrypted attribute register inside the tamper resistant processor, so that it is possible to share the encrypted data region safely.

Abstract: In a method for using the shared library in a tamper resistant microprocessor, the execution code of the shared library is protected because the shared library itself is processed as a task which has a single identifier, and the instruction key for encrypting/decrypting the shared library is recorded at a location within the microprocessor corresponding to that identifier.

Abstract: A computer readable storage medium encoded with computer instructions for causing a tamper resistant microprocessor which has a function for decrypting and executing encrypted codes and a table formed by a plurality of regions for storing a plurality of encryption keys corresponding to at least one program and at least one shared library to be called up by the at least one program, to use a shared library called up from a calling source program, the instructions including the steps of causing the tamper resistant microprocessor to create a task for the shared library, causing the tamper resistant microprocessor to allocate a task identifier to the task, causing the tamper resistant microprocessor to acquire an instruction key from a header of the shared library, causing the tamper resistant microprocessor to store the instruction key into a region of the table corresponding to the task identifier allocated to the task for the shared library in the microprocessor, causing the tamper resistant microprocessor to

Abstract: A scheme for distributing executable programs through a network from a program distribution device to a client device having a tamper resistant processor which is provided with a unique secret key and a unique public key corresponding to the unique secret key in advance is disclosed. In this scheme, a first communication path is set up between the program distribution device and the client device, and a second communication path directly connecting the program distribution device and the tamper resistant processor is set up on the first communication path. Then, the encrypted program is transmitted from the program distribution device to the tamper resistant processor through the second communication path.

Abstract: In an inner memory type tamper resistant microprocessor, a requested secret protection attribute requested for each access target memory page by a task is set and stored exclusively from other tasks, at a time of reading a program into memory pages and executing the program as the task, and a memory secret protection attribute is set and stored for each access target memory page by the task, at a time of executing the task. Then, an access to each access target memory page is refused when the requested secret protection attribute for each access target memory page and the memory secret protection attribute for each access target memory page do not coincide.

Abstract: A processor having a program protection function, which makes behavior analysis of protected programs difficult and allows improvement in the current program protection level, which is attained by prohibiting reading out/rewriting of instruction codes, is provided. The processor having a program protection function is a processor core module, which protects programs by allowing only reading out of instructions in a decrypted, protected plain text program for being executed and which is constituted by a detecting unit for detecting whether or not an instruction in a protected program is being executed and a prohibiting unit for prohibiting generation of trace information for an instruction being executed when the detecting unit detects that an instruction in a protected program is being executed.

Abstract: The disclosed communication node has a function for recognizing one communication node on the first network as one of constituent elements in own communication node, and a function for disclosing an own configuration information regarding the constituent elements as recognized above, to another communication node on the second network. Also, the disclosed communication terminal has a function for disclosing functions in the own communication terminal as Sub Units in an AV/C (Audio/Visual Control) protocol executed on an IEEE 1394 bus, and a function for receiving at least a part of information regarding Sub Units existing in the communication node on the second network with which it is communicating.

Abstract: In a device authentication management system in which a device acquires a secret information from an authentication management unit and carries out an authentication in order to carry out communications with another device by using the secret information, the authentication management unit generates the secret information that contains a first authentication information for carrying out communications between the authentication management unit and the device, and a second authentication information for carrying out communications between the device and the another device; carries out the authentication in order to carry out communications with the device, by using the first authentication information; and transmits the second authentication information according to the authentication.

Abstract: In a microprocessor that internally has a microprocessor specific secret key, a key management unit is provided to carry out a key registration for reading out from an external memory a distribution key that is obtained in advance by encrypting the instruction key by using a public key corresponding to the secret key, decrypting the distribution key by using the secret key to obtain the instruction key, and registering the instruction key in correspondence to a specific program identifier for identifying the program into a key table, and to notify a completion of the key registration to the processor core asynchronously by interruption when the key registration is completed.