Abstract: A method of forming a co-axial interconnect line in a dielectric layer is provided. The method includes defining a trench in the dielectric layer and then forming a shield metallization layer within the trench. After forming the shield metallization layer, a conformal oxide layer is deposited within the shield metallization layer. A center conductor is then formed within the conformal oxide layer. Once the center conductor is formed, a fill oxide layer is deposited over the center conductor. A cap metallization layer is then formed over the fill oxide layer and is in contact with the shield metallization layer.

Abstract: A method for making a semiconductor device with integrated CMOS circuitry and RF circuitry fabricated over a semiconductor wafer, and a semiconductor device with integrated CMOS circuitry and RF circuitry fabricated over a semiconductor wafer is provided. The method includes forming a lower metallization layer and a lower dielectric layer over the lower metallization layer. A metallization line is formed over the lower dielectric layer with an upper dielectric layer over the metallization line. An upper metallization layer is then formed over the upper dielectric layer. After this is completed, oxide spacers are formed along the sides of the lower dielectric layer, the metallization line, and the upper dielectric layer. Finally, an encapsulating metallization layer is formed over the oxide spacers such that the lower metallization layer, the upper metallization layer and the encapsulating metallization layer define an outer shield and the metallization line defines an inner conductor of an RF line.

Abstract: A method of using a gaseous environment providing improved control of CMP process. In one embodiment, the method comprises several steps. One step involves placing a semiconductor wafer onto a polishing pad of a CMP machine. A subsequent step dispenses a slurry onto the polishing pad. Another step provides a blanket of gas that displaces the ambient atmosphere surrounding the semiconductor wafer. In another step, the blanket of gas is maintained around the semiconductor wafer during the CMP operation.

Abstract: A waveguide structure and method of making a waveguide for communicating optical signals is provided. The waveguide structure is made using standard CMOS fabrication operations and is integrated on the same chip having digital CMOS circuitry. An example method of making the waveguide includes forming a contact through a dielectric layer down to a substrate and coating sidewalls of the contact with a first metallization coating. The contact is then filled with a dielectric material. A partial waveguide structure is formed over the first metallization coating and the dielectric material of the contact. The partial waveguide structure is defined by a waveguide dielectric structure and a second metallization coating that is defined over the waveguide dielectric structure. A third metallization coating is then formed to define spacers along sides of the partial waveguide structure, the first metallization coating, the second metallization coating.

Abstract: An apparatus for reducing interconnect resistance using optimized trench geometry. One embodiment comprises an interconnect line and an interconnect well. The interconnect line, comprised of a conductive material, has a depth and exists in a first circuit layer of a multilayered Integrated Circuit (IC). The interconnect well is coupled to the interconnect line and is insulated from other conductive materials in the first circuit layer, and in the plurality of subsequent adjacent layers. The interconnect well has a depth in said multilayered IC that exceeds said depth of said interconnect line.

Abstract: Disclosed are techniques to provide an integrated circuit, including the provision of improved integrated circuit isolation structures. The techniques include forming a number of trenches in an integrated circuit substrate to define a number of substrate regions that are to be electrically isolated from one another. A dielectric material is deposited in the trenches by exposure to a high density plasma having a first deposition-to-etch ratio. The high density plasma is adjusted to a second deposition-to-etch ratio greater than the first ratio to accumulate the dielectric material on the substrate after at least partially filling the trenches. A portion of the dielectric material is removed to planarize the workpiece. A number of components, such as insulated gate field effect transistors, may be subsequently formed in the substrate regions between the trenches.

Abstract: A method of using polish stop film to control dishing during copper chemical mechanical polishing. In one embodiment, the method comprises several steps. One step involves depositing a polish stop layer above a metal layer disposed on a semiconductor wafer. Another step involves placing the semiconductor wafer onto a polishing pad of a chemical mechanical polishing machine. A further step involves removing the metal layer of the semiconductor wafer and also preferentially removing the polish stop layer using a chemical mechanical polishing process. The benefit of the polish stop layer is to prevent dishing of the metal layer within the trench. Another step involves ceasing the chemical mechanical polishing process when the metal layer is removed from desired areas of the semiconductor wafer and the semiconductor wafer is substantially planar.

Abstract: A primary layer deposited over a secondary layer is planarized. A chemical mechanical polishing process is performed using a slurry which targets the primary layer. Then, chemical etching is performed using a chemical wet etchant which targets the secondary layer. The method is used, for example, when making connections to a lower layer through an insulating layer. Plug holes are formed through the insulating layer to the lower layer. Then the secondary layer is deposited. The secondary layer acts as a barrier layer or a glue layer.

Abstract: An apparatus for optimizing electrical currents to improve copper plating uniformity on a semiconductor wafer is disclosed. The use of multiple anodes of the embodiment provides for variable electrical currents to the semiconductor wafer, the variable feature of the variable electrical currents compensating for non-uniform electroplating characteristics.

Abstract: A method of using polish stop film to control dishing during copper chemical mechanical polishing. In one embodiment, the method comprises several steps. One step involves depositing a polish stop layer above a metal layer disposed on a semiconductor wafer. Another step involves placing the semiconductor wafer onto a polishing pad of a chemical mechanical polishing machine. A further step involves removing the metal layer of the semiconductor wafer and also preferentially removing the polish stop layer using a chemical mechanical polishing process. The benefit of the polish stop layer is to prevent dishing of the metal layer within the trench. Another step involves ceasing the chemical mechanical polishing process when the metal layer is removed from desired areas of the semiconductor wafer and the semiconductor wafer is substantially planar.

Abstract: A complementary conditioning system for use in chemical mechanical polishing (CMP). The present invention functions with a CMP machine adapted for polishing a semiconductor wafer having tungsten components fabricated thereon. A polishing pad is mounted on the CMP machine. The polishing pad has a polishing surface configured for polishing the semiconductor wafer and its tungsten components. The performance of the polishing surface is characterized by a polishing efficiency. A complementary end-effector is mounted on the CMP machine. The complementary end-effector is adapted to chemically complement the tungsten components on the semiconductor wafer. The complementary end-effector is further adapted to contact the polishing surface and improve the polishing efficiency by chemically enhancing the polishing surface, thereby obtaining a more efficient removal rate for the chemical mechanical polishing.

Abstract: A system for film thickness sample assisted surface profilometry. The sample assisted surface profilometry system of the present invention is utilized to determine an absolute topography variation of a surface of a layer of an integrated circuit with respect to the surface of an underlying layer of known height orientation. The present invention is comprised of a thickness measurement tool for measuring a thickness of the layer at sample points. The thickness measurement tool measures a thickness sample, wherein the thickness sample characterizes the thickness of the layer over the known layer. A surface profilometry tool is coupled to the thickness measurement tool to receive the thickness measurements of the sample points. The surface profilometry tool is utilized to measure relative topography variations of the surface of the layer.

Abstract: A method and apparatus for detecting the presence of gaseous impurities, notably oxygen, in a gas mixture that flows over an IC wafer in an etcher during the etching process. The method is based upon the discovery that the ratio of the etch rate of spin-on-glass material to the etch rate of other materials, such as plasma-enhanced chemical vapor deposition (PECVD oxide) materials, varies in a predictable manner with the amount of oxygen contaminating the gas mixture. The standard ratio, in the absence of oxygen, is determined for a given set of processing conditions by first etching an SOG wafer, then etching a PECVD oxide material wafer, measuring the amount of material etched in each case, and from that calculating the respective etch rates, and finally taking the ratio of the two calculated etch rates. This standard ratio is used as the benchmark for future tests.

Abstract: An integrated circuit (IC) fabrication process involves forming electronic devices on a semiconductor substrate. A metal layer is deposited thereover and then patterned to interconnect the semiconductor devices. A dielectric layer is deposited over the metal layer and substrate. The dielectric layer is etched back to prepare for the deposition of additional metal and dielectric layers. The etched surface is scanned by an atomic force microscope (AFM) to gather data representing the wafer surface roughness. The data is evaluated by a computer to generate at least one surface roughness signal. Depending on the value of the surface roughness signal, the IC fabrication process continues with the next step, a remedial action is taken, the IC fabrication process is adjusted for subsequent wafers, or the wafer is discarded.

Abstract: An integrated circuit fabrication method begins with semiconductor devices formed on a substrate. A patterned metal layer is deposited on the substrate to connect the semiconductor devices. A nitride layer is deposited over the metal layer and substrate. The nitride layer topography comprises hills located over metal regions and valleys located over non-metal regions. Spin-on-glass (SOG) is deposited over the nitride layer, thereby filling the valleys and covering the hills. The SOG layer and the nitride layer hills are etched back at substantially the same etch rate, using plasma etching, to form a planar surface. An oxide layer is then deposited over the planar surface to encapsulate the semiconductor devices, metal layer, nitride layer and SOG layer. Vias may then be etched through the oxide layer and the nitride layer to expose portions of the underlying metal layer and facilitate upper layer metal connections thereto.

Abstract: A method for improved planarization of surface topographies encountered in semiconductor processing that involve the etch-back of exposed surfaces of an oxide of silicon and a spin-on-glass. The oxide of silicon is chosen to be oxygen-deficient and thus silicon-rich, with a spectroscopically-defined silicon richness coefficient CSR that is greater than 0, and preferably greater than 0.005. A fluorine-containing process gas such as CHF.sub.3 combined with one or more of CF.sub.4, C.sub.2 F.sub.6 and SF.sub.6 can be used in the etch chemistry. Sensitivity of the etch rate to certain parameters, such as the relative surface area of the exposed oxide of silicon and the fraction of fluorine present, is either reduced or eliminated. Improvement and better control of planarization is achieved by the process, resulting in a widening of the etch-back process window.