Abstract: A transform function represented by at least n points that define n-1 regions is determined based at least in part on a first set of values associated with a display frame and a maximum average contrast function. The n points can be determined in response to a change in an average contrast of the display frame compared to an average contrast of a previous display frame exceeding a predetermined threshold. The first set of values is converted to a corresponding second set of values based on the transform function. A backlight control signal is generated based on an average contrast of the second set of values, whereby the backlight control signal is configured to control an intensity of a backlight of a display. Further, a video signal is generated based on the second set of values, whereby the video signal configured to drive the display.

Abstract: An n bit D/A decoder is formed using P-type and N-type transistor switches, instead of convention CMOS switches. Each P-type and N-type switch may be formed of fewer transistors than those used to form a CMOS switch, thereby reducing the overall transistor count. The decoder may be used to decode digital values to non-linear GAMMA corrected analog output voltages.

Abstract: A method and apparatus for detecting an error compares a hardwired reference value to a corresponding predetermined value and generates an error indication in response to a change in the predetermined value. In one embodiment, the predetermined value is set to be the same as the hardwired reference value and in response to an electrostatic discharge event or any other suitable cause of error, the predetermined value changes so that a comparison indicates that an error has occurred. An error indication is then generated which may be, for example, an interrupt to recovery logic that generates recovery control information to reset a functional block that was corrupted or to perform in an entire chip reset if desired.

Abstract: A graphics multi-media integrated circuit (GMIC) is connected to a host processor over two serial links: a half duplex bi-directional serial link which accords to a protocol defined for a display serial interface, and a uni-directional serial link which accords to a compatible protocol defined for a camera serial interface. The GMIC receives packets according to the protocol from the host over the half duplex bi-directional serial link and processes these packets. The GMIC sends packets according to the protocol to the host over the uni-directional serial link. A packet from the host can request a processing operation by the GMIC or can initiate a memory operation at the memory of the GMIC. The GMIC can also send packets to the host to initiate a memory operation at the memory of the host.

Abstract: To derive a Hamming code to manage data errors a set of at least four parity bit positions is selected for parity bits which will protect a set of data bits (where each data bit has a data bit position in the data bit set). A syndrome is determined for each data bit position. This involves selecting a unique sub-set of at least three parity bit positions. The unique sub-set shares at least one parity bit position with at least one other unique sub-set of at least three parity bit positions. A parity bit value may then be calculated for each parity bit position based on the determined syndromes. The header of a packet may be provided with a word which defines the length of the packet and an error management code generated utilizing this word so that errors in the word may be detected and, possibly, corrected.

Abstract: A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output (IO) controller via a high-speed PCI bus. The IO controller interfaces to the system graphics controller via the high-speed PCI bus. The IO controller includes a lower speed PCI port controlled by an arbiter within the IO controller. Generally, the low speed PCI arbiter of the IO controller will interface to standard 33 MHz PCI cards. In addition, the IO controller interfaces to an external storage device, such as a hard drive, via either a standard or a proprietary bus protocol. A unified system/graphics memory which is accessed by the system/graphics controller. The unified memory contains both system data and graphics data. In a specific embodiment, two channels, CH0 and CH1 access the unified memory.

Abstract: A buffer is associated with each of a plurality of data lanes of a multi-lane serial data bus. Data words are timed through the buffers of active ones of the data lanes. Words timed through buffers of active data lanes are merged onto a parallel bus such that data words from each of the active data lanes are merged onto the parallel bus in a pre-defined repeating sequence of data lanes. This approach allows other, non-active, data lanes to remain in a power conservation state.

Abstract: A block-based image compression method and encoder/decoder circuit compresses a plurality of pixels having corresponding original color values and luminance values in a block according to different modes of operation. The encoding circuit includes a luminance-level-based representative color generator to generate representative color values for each of a plurality of luminance levels derived from the corresponding luminance levels to produce at least a block color offset value and a quantization value. According to mode zero, each of the pixels in the block is associated with one of the plurality of generated representative color values to generate error map values and a mode zero color error value. According to mode one, representative color values for each of at least three luminance levels are also generated to produce at least three representative color values, corresponding bitmap values and a mode one color error value.

Abstract: A target pixel and surrounding pixels corresponding to the target pixel are obtained from a digitally represented image. A bilateral high pass filtering kernel is determined based at least in part upon the target pixel and the surrounding pixels. A high pass spatial filtering kernel is provided and multiplied with the high pass photometric filtering kernel to provide a bilateral high pass filtering kernel. The resulting bilateral high pass filtering kernel is thereafter applied to the target pixel and the surrounding pixels to provide a filtered pixel. When it is desirable to combine noise filtering capabilities with sharpening capabilities, the bilateral high pass filter of the present invention may be combined with a bilateral low pass filtering kernel to provide a combined noise reduction and edge sharpening filter. The present invention may be advantageously applied to a variety of devices, including cellular telephones that employ image sensing technology.

Abstract: To derive a Hamming code to manage data errors a set of at least four parity bit positions is selected for parity bits which will protect a set of data bits (where each data bit has a data bit position in the data bit set). A syndrome is determined for each data bit position. This involves selecting a unique sub-set of at least three parity bit positions. The unique sub-set shares at least one parity bit position with at least one other unique sub-set of at least three parity bit positions. A parity bit value may then be calculated for each parity bit position based on the determined syndromes. The header of a packet may be provided with a word which defines the length of the packet and an error management code generated utilizing this word so that errors in the word may be detected and, possibly, corrected.

Abstract: A buffer is associated with each of a plurality of data lanes of a multi-lane serial data bus. Data words are timed through the buffers of active ones of the data lanes. Words timed through buffers of active data lanes are merged onto a parallel bus such that data words from each of the active data lanes are merged onto the parallel bus in a pre-defined repeating sequence of data lanes. This approach allows other, non-active, data lanes to remain in a power conservation state.

Abstract: An apparatus and method are disclosed wherein a depth map is generated using a single camera (e.g., single lens of a camera) and multiple images are captured by the camera. In one example, a single digital camera is used to capture a set of images corresponding to a set of lens positions based on lens position data. In this example, the lens position data may be either uniform or nonuniform lens position data. The method and apparatus determines focus metric information for each of a plurality of regions of interest in each image of a set. A determination is made of a best lens position for each of the regions of interest based on the focus metric information from the images in the set and are stored as data in a depth map. Image generation operations are then performed based on the generated depth map, such as determining whether or not to use a flash to capture a final image, to determine a type of color operation to be performed on the final image, or any other suitable image generation operation.

Abstract: A method and apparatus improves an auto focus system by altering, such as by positioning, at least one lens of a digital camera to a plurality of predetermined nonuniform lens positions corresponding to predetermined nonuniform lens position data. The method and apparatus selects a final lens position for the lens based on the predetermined nonuniform lens position data. In one example, a fixed number of predetermined nonuniform lens positions define a set of lens positions used to capture images during an auto focus operation. A final image is captured using a final lens position. The final lens position is determined by comparing focus metric information from each of the frames obtained at the various predetermined nonuniform focus lens positions and selecting the frame with, for example, the best focus metric as the lens position to be used for the final picture or image capture.

Abstract: A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output (IO) controller via a high-speed PCI bus. The IO controller interfaces to the system graphics controller via the high-speed PCI bus. The IO controller includes a lower speed PCI port controlled by an arbiter within the IO controller. Generally, the low speed PCI arbiter of the IO controller will interface to standard 33 MHz PCI cards. In addition, the IO controller interfaces to an external storage device, such as a hard drive, via either a standard or a proprietary bus protocol. A unified system/graphics memory which is accessed by the system/graphics controller. The unified memory contains both system data and graphics data. In a specific embodiment, two channels, CH0 and CH1 access the unified memory.

Abstract: A method and apparatus for camera shake effect image stabilization determines a most favorable image sharpness metric out of image sharpness metrics from a plurality of images that were captured at a same lens position. A final image is selected based on the most favorable image sharpness metric.

Abstract: The present invention provides a method and apparatus for image processing using a graphics processor in a handheld device including a first memory device receiving a video input signal containing encoded video frame having a plurality of portions of encoded video frame data. The first memory device has a storage capacity less than all of the plurality portions of the encoded video frame data. The method and apparatus further includes the graphics processor coupled to the first memory device, wherein the graphics processor receives the first portion of the encoded video frame data and generates a first graphics portion. A second memory device receives the first graphics portion and stores the first graphics portion therein. As such, the encoded video frame is processed on a portion-by-portion basis using the first memory device and the second memory device in conjunction with the graphics processor.

Abstract: A method and apparatus for image compositing in an apparatus a device in which available memory is at a premium are disclosed. The apparatus includes a first memory that receives a video input signal, in multiple portions. The first memory has a storage capacity less than the entire video image. Data within the first memory is encoded to form encoded video image portions. The entire image is thus encoded, video image portion by video image portion. A second image is combined with image portions in the first memory prior encoding such video image portions. The apparatus may, for example, be an electronic component or components forming a video or image processing pipeline, used in a portable device.

Abstract: An n bit D/A decoder is formed using P-type and N-type transistor switches, instead of convention CMOS switches. Each P-type and N-type switch may be formed of fewer transistors than those used to form a CMOS switch, thereby reducing the overall transistor count. The decoder may be used to decode digital values to non-linear GAMMA corrected analog output voltages.

Abstract: An n bit D/A decoder is formed using P-type and N-type transistor switches, instead of convention CMOS switches. Each P-type and N-type switch may be formed of fewer transistors than those used to form a CMOS switch, thereby reducing the overall transistor count. The decoder may be used to decode digital values to non-linear GAMMA corrected analog output voltages.

Abstract: A portable device includes a controller that is responsive to a remaining power capacity of the battery, and a power consumption level of the portable device and based on user prioritized functional processing capability features, dynamically controls functional processing capability features of the device. The controller provides power for a higher priority feature at the expense of a lower priority functional processing capability feature consistent with the user prioritized functional processing capability features. A wireless portable device is also disclosed that includes a wireless signal strength determinator that determines a received signal strength of the wireless device and a controller that adjusts the functional processing capability feature of the wireless device based on the determined received signal strength and based on battery capacity information.