Abstract: Proving for a framework for propagating priorities to a memory subsystem in a computing system environment is disclosed herein. By way of example, a memory access handler is provided for managing memory access requests and determining associated priorities. The memory access handler includes logic configured for propagating memory requests and the associated priorities to lower levels of a computer hierarchy. A memory subsystem receives the memory access requests and the priorities.

Abstract: Computerized payment method using short, temporary, transaction ID (TID) symbols for secure payer (customer) financial transactions. Payees (e.g. merchants) register their unique ID telecommunications devices (e.g. Smartphone and phone number), and financial institution a payment server. When a payee (merchant) and wish to do a financial transaction, the payee requests a TID from the server for that amount. The server sends a TID to the payee, which the payee then communicates to the payer. The payer in turn relays this TID to the server, which validates the transaction using the payer device. The server then releases funds to the payee. The server preserves records for auditing, but security is enhanced because the merchant never directly accesses the customer's financial account. Use of GPS coordinates and/or payer provided Group IDs may also be used to reduce the number of symbols used in the TID while continuing to ensure uniqueness.

Abstract: Method of controlling playback of Internet web page video on remote or high quality video displays using a remote control device, such as a smart phone. The method runs a first client browser on the remote control device, which in turn sends commands to a proxy browser with a data buffer. In response to user commands from the remote control device, the proxy browser retrieves and buffers video and non-video web page data from Internet servers, and sends this data to the remote control device. Upon user command, the proxy browser also sends selected buffered data to a second client browser that is connected to the remote or high quality video display. Media player playback commands on the remote control are echoed to a second media player on the second client browser, resulting in good synchronization between devices. Various compression, IP address adjustment, and public key methods are also discussed.

Abstract: Method of using a computerized smartphone to navigate remote auto attendant telephony systems with a menu structure. The auto attendant's menu structure is put into an online computer database. The caller uses the smartphone to call and establish a voice channel with remote auto attendant telephony system (using the telephone number of that system), software applications running on the caller's smartphone communication device intercept the telephone number and along with the voice channel, also establish a data channel with the online computer accessible database. The caller's smartphone retrieves at least some of the menu structure of the auto attendant telephony system through this data channel, and displays at least some of the menu structure of the remote auto attendant telephony system on the graphical user interface of the user's smartphone synchronized, with the audio delivery of the menu structure, thus facilitating interactions with the auto attendant system.

Abstract: An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.

Abstract: Systems and methods that facilitate multi-word atomic operation support for systems on chip are described. One method involves: receiving an instruction associated with a calling process, and determining a first memory width associated with execution of the instruction based on an operator of the instruction and a width of at least one operand of the instruction. The instruction can be associated with an atomic operation. In some embodiments, the instruction contains a message having a first field identifying the operator and a second field identifying the operand.

Abstract: A processor of an aspect includes a register file including a first register to hold a first packed data including a first low data element and a first high data element, a second register to hold a second packed data including a second low data element and a second high data element, and a third register. The processor also includes a decoder to decode an unpack instruction. The processor also includes a functional unit coupled with the decoder and the register file. The functional unit, in response to the decoder decoding the unpack instruction, is to transfer the first low data element to a high position of the third register and the second low data element to a low position of the third register.

Abstract: An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.

Abstract: An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.

Abstract: Method of using a computerized smart phone to navigate remote auto attendant telephony systems with a menu structure. The auto attendant's menu structure is put into an online computer database. When the caller uses the smart phone to call and establish a voice channel with remote auto attendant telephony system (using the telephone number of that system), software applications running on the caller's smart phone communication device intercept the telephone number and along with the voice channel, also establish a data channel with the online computer accessible database. The caller's smart phone can then retrieve at least some of the menu structure of the auto attendant telephony system through this data channel. This application software can then display at least some of the menu structure of the remote auto attendant telephony system on the graphical user interface of the user's smart phone synchronized with the audio delivery of the menu structure, facilitating interactions with the auto attendant system.

Abstract: A processor capable of secure execution. The processor contains an execution unit and secure partition logic that secures a partition in memory. The processor also contains cryptographic logic coupled to the execution unit that encrypts and decrypts secure data and code.

Abstract: A processor capable of secure execution. The processor contains an execution unit and secure partition logic that secures a partition in memory. The processor also contains cryptographic logic coupled to the execution unit that encrypts and decrypts secure data and code.

Abstract: A processor capable of secure execution. The processor contains an execution unit and secure partition logic that secures a partition in memory. The processor also contains cryptographic logic coupled to the execution unit that encrypts and decrypts secure data and code.

Abstract: A processor capable of secure execution. The processor contains an execution unit and secure partition logic that secures a partition in memory. The processor also contains cryptographic logic coupled to the execution unit that encrypts and decrypts secure data and code.

Abstract: A processor capable of secure execution. The processor contains an execution unit and secure partition logic that secures a partition in memory. The processor also contains cryptographic logic coupled to the execution unit that encrypts and decrypts secure data and code.

Abstract: A processor capable of secure execution. The processor contains an execution unit and secure partition logic that secures a partition in memory. The processor also contains cryptographic logic coupled to the execution unit that encrypts and decrypts secure data and code.

Abstract: An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.

Abstract: Provided is an end-to-end flow control management for a system on chip interface. As tokens are injected into agents arranged in a computer network, the input point for the token is dynamically changed such that tokens are not always injected into the same agent. Additionally or alternatively, as tokens are injected into a token ring, the tokens are initially not activated until a predetermined event occurs (e.g., after a specific number of hops). Additionally or alternatively, also provided is a free pool manager that can keep at least some high priority slots available by consuming lower priority slots first.

Abstract: Computerized payment method using short, temporary, transaction ID (TID) symbols for secure payer (customer) financial transactions. Payees (e.g. merchants) register their unique ID telecommunications devices (e.g. Smartphone and phone number), and financial institution a payment server. When a payee (merchant) and wish to do a financial transaction, the payee requests a TID from the server for that amount. The server sends a TID to the payee, which the payee then communicates to the payer. The payer in turn relays this TID to the server, which validates the transaction using the payer device. The server then releases funds to the payee. The server preserves records for auditing, but security is enhanced because the merchant never directly accesses the customer's financial account. Use of GPS coordinates and/or payer provided Group IDs may also be used to reduce the number of symbols used in the TID while continuing to ensure uniqueness.

Abstract: An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.