Abstract: An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.

Abstract: A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.

Abstract: A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.

Abstract: A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.

Abstract: An input lookup key is hashed and the hashed key divided into stride bits into a multi-level Trie structure. A compression function logically combines the stride bits to generate the compressed index bits into the stride tables. The bucket in the last stride table found by the hashed key may have several keys that collide at the same hash value. Discriminant bits are read from the key and select a stored key in the bucket table for verification of its result. Since the hashed key is a compression of the longer input key, more information is contained per bit of the hashed key than in the long key. The multi-stride lookup is performed first on the hashed key, allowing a faster convergence to the lookup result. The first stride can index a single hash table, with the remaining hash bits and discriminant bits used to select from among colliding keys.

Abstract: An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.

Abstract: Method of controlling playback of Internet web page video on remote or high quality video displays using a remote control device, such as a smart phone. The method runs a first client browser on the remote control device, which in turn sends commands to a proxy browser with a data buffer. In response to user commands from the remote control device, the proxy browser retrieves and buffers video and non-video web page data from Internet servers, and sends this data to the remote control device. Upon user command, the proxy browser also sends selected buffered data to a second client browser that is connected to the remote or high quality video display. Media player playback commands on the remote control are echoed to a second media player on the second client browser, resulting in good synchronization between devices. Various compression, IP address adjustment, and public key methods are also discussed.

Abstract: A processor capable of secure execution. The processor contains an execution unit and secure partition logic that secures a partition in memory. The processor also contains cryptographic logic coupled to the execution unit that encrypts and decrypts secure data and code.

Abstract: An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.

Abstract: A processor capable of secure execution. The processor contains an execution unit and secure partition logic that secures a partition in memory. The processor also contains cryptographic logic coupled to the execution unit that encrypts and decrypts secure data and code.

Abstract: An input lookup key is hashed and the hashed key divided into stride bits into a multi-level Trie structure. A compression function logically combines the stride bits to generate the compressed index bits into the stride tables. The bucket in the last stride table found by the hashed key may have several keys that collide at the same hash value. Discriminant bits are read from the key and select a stored key in the bucket table for verification of its result. Since the hashed key is a compression of the longer input key, more information is contained per bit of the hashed key than in the long key. The multi-stride lookup is performed first on the hashed key, allowing a faster convergence to the lookup result. The first stride can index a single hash table, with the remaining hash bits and discriminant bits used to select from among colliding keys.

Abstract: Method of using a computerized smart phone to navigate remote auto attendant telephony systems with a menu structure. The auto attendant's menu structure is put into an online computer database. When the caller uses the smart phone to call and establish a voice channel with remote auto attendant telephony system (using the telephone number of that system), software applications running on the caller's smart phone communication device intercept the telephone number and along with the voice channel, also establish a data channel with the online computer accessible database. The caller's smart phone can then retrieve at least some of the menu structure of the auto attendant telephony system through this data channel. This application software can then display at least some of the menu structure of the remote auto attendant telephony system on the graphical user interface of the user's smart phone synchronized with the audio delivery of the menu structure, facilitating interactions with the auto attendant system.

Abstract: Method of using a computerized smart phone to navigate remote auto attendant telephony systems with a menu structure. The auto attendant's menu structure is put into an online computer database. When the caller uses the smart phone to call and establish a voice channel with remote auto attendant telephony system (using the telephone number of that system), software applications running on the caller's smart phone communication device intercept the telephone number and along with the voice channel, also establish a data channel with the online computer accessible database. The caller's smart phone can then retrieve at least some of the menu structure of the auto attendant telephony system through this data channel. This application software can then display at least some of the menu structure of the remote auto attendant telephony system on the graphical user interface of the user's smart phone synchronized with the audio delivery of the menu structure, facilitating interactions with the auto attendant system.

Abstract: Method of controlling playback of Internet web page video on remote or high quality video displays using a remote control device, such as a smart phone. The method runs a first client browser on the remote control device, which in turn sends commands to a proxy browser with a data buffer. In response to user commands from the remote control device, the proxy browser retrieves and buffers video and non-video web page data from Internet servers, and sends this data to the remote control device. Upon user command, the proxy browser also sends selected buffered data to a second client browser that is connected to the remote or high quality video display. Media player playback commands on the remote control are echoed to a second media player on the second client browser, resulting in good synchronization between devices. Various compression, IP address adjustment, and public key methods are also discussed.

Abstract: A processor capable of secure execution. The processor contains an execution unit and secure partition logic that secures a partition in memory. The processor also contains cryptographic logic coupled to the execution unit that encrypts and decrypts secure data and code.

Abstract: An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to pack the packed data responsive to a pack instruction received by the decoder. A first packed data element and a second packed data element are received from the first source register. A third packed data element and a fourth packed data element are received from the second source register. The circuit packs packing a portion of each of the packed data elements into a destination register resulting with the portion from second packed data element adjacent to the portion from the first packed data element, and the portion from the fourth packed data element adjacent to the portion from the third packed data element.

Abstract: A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.

Abstract: A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.

Abstract: A system and method are provided for stacking storage drives in a network attached storage (NAS) system. The method provides a NAS stacking network including at least a first and second stackable building block (SBB), where each SBB includes a head, with an embedded processor and storage application, and a storage drive including client files. The method connects a first interface of the first SBB to a client computer device via a LAN switch, and connects a second interface of the first SBB to the first interface of the second SBB. A directory is built of client files stored in the first and second SBBs. The directory is maintained in both the first and second SBBs. In one aspect, the first SBB, acting as a primary SBB, provides access to NAS stacking network directory structure in response to an inquiry from a client computer connected to the LAN switch.

Abstract: A processor. The processor includes a first register for storing a first packed data, a decoder, and a functional unit. The decoder has a control signal input. The control signal input is for receiving a first control signal and a second control signal. The first control signal is for indicating a pack operation. The second control signal is for indicating an unpack operation. The functional unit is coupled to the decoder and the register. The functional unit is for performing the pack operation and the unpack operation using the first packed data. The processor also supports a move operation.