Abstract: A self-aligned metal electrode sensor structure. The self-aligned metal electrode sensor structure includes a substrate which includes electronic circuitry. An interconnect structure is formed adjacent to the substrate. The interconnect structure includes conductive interconnect vias which pass through the interconnect structure. A sensor is formed adjacent to the interconnect structure. The sensor includes a pixel metallization section and a doped layer electrode. The pixel metallization section is electrically connected to the interconnect via. The pixel metallization section includes an outer surface which is substantially planar. The doped layer electrode includes an inner surface adjacent to the outer surface of the pixel metallization section. The entire inner surface of the doped layer electrode is substantially planar. A transparent conductive layer is formed adjacent to the sensor. The interconnect via and the transparent conductive layer electrically connect the electronic circuitry to the sensor.

Abstract: A self-aligned metal electrode sensor structure. The self-aligned metal electrode sensor structure includes a substrate which includes electronic circuitry. An interconnect structure is formed adjacent to the substrate. The interconnect structure includes conductive interconnect vias which pass through the interconnect structure. A sensor is formed adjacent to the interconnect structure. The sensor includes a pixel metallization section and a doped layer electrode. The pixel metallization section is electrically connected to the interconnect via. The pixel metallization section includes an outer surface which is substantially planar. The doped layer electrode includes an inner surface adjacent to the outer surface of the pixel metallization section. The entire inner surface of the doped layer electrode is substantially planar. A transparent conductive layer is formed adjacent to the sensor. The interconnect via and the transparent conductive layer electrically connect the electronic circuitry to the sensor.

Abstract: A highly-efficient thermal inkjet printhead. The printhead includes a primary layer of polycrystalline silicon (preferably doped) having at least one portion thereof which functions as an ink expulsion resistor. Positioned over and above the primary layer is a secondary layer of material having at least one section produced from a selected metal silicide compound and at least another section fabricated from undoped polycrystalline silicon. The metal silicide-containing section functions as an interconnect structure and is operatively connected to the resistor in the primary layer (which is positioned beneath the secondary layer). The undoped polycrystalline silicon section is at least partially aligned over and above the resistor. As a result, the resistor is “buried” beneath the secondary layer and the various portions thereof. This system provides improved reliability, greater dimensional simplicity, optimized electrical/thermal properties, and superior versatility.

Abstract: A highly-efficient thermal inkjet printhead. The printhead includes at least one doped polycrystalline silicon resistor which communicates with an external signal source using a unique interconnection system. Specifically, a primary layer of electrically conductive material (optimally a metal silicide) is connected to the resistor. An additional layer of electrically conductive material is attached to and above the primary layer. The additional layer terminates at a position which is spaced outwardly and apart from the resistor to form a gap therebetween. However, the underlying primary layer electrically links the additional layer to the resistor. Alternatively, a dielectric layer is attached to and above the primary layer, with the additional layer being secured to the dielectric layer. At least one electrically conductive contact member is provided within the dielectric layer to link the primary and additional layers.

Abstract: A method for fabricating dual gate dielectric layers on a semiconductor substrate involves utilizing a single photolithographic step to form layer stacks having two different gate dielectric layers and associated polysilicon layers, and then utilizing a physical planarization process to remove excess polysilicon and silicon oxide. According to the method, a first gate dielectric is formed on the first and second device areas of a substrate. A first polysilicon layer is deposited onto the first gate dielectric, and portions of the first polysilicon layer are removed utilizing a photolithographic process. The first gate dielectric is removed over the second device area, and a second, thinner gate dielectric is formed over the second device area. A second polysilicon layer is formed over the second gate dielectric and over the first polysilicon layer.

Abstract: A structure and a method for providing structural stability at an interface between two poorly adhering layers in a semiconductor device involve providing anchoring channels in one of the poorly adhering layers through which the other poorly adhering layer can be anchored to a third layer. Specifically, the structure and method are applicable to a three-layer stack having a top layer of amorphous silicon, a middle layer of titanium nitride, and a bottom layer of oxide. In order to reduce susceptibility to delamination between the amorphous silicon layer and the titanium nitride layer, the anchoring channels are created in the titanium nitride layer to allow the amorphous silicon to attach to the oxide layer. Because the amorphous silicon layer and the oxide layer exhibit good adhesion between each other, delamination between the amorphous silicon layer and the titanium nitride layer is minimized.

Abstract: An array of active pixel sensors. The array of active pixel sensors includes a substrate that includes electronic circuitry. An interconnect structure is formed adjacent to the substrate. The interconnect structure includes a plurality of conductive vias. A plurality of conductive guard rings are formed adjacent to the interconnect structure. Each conductive guard ring is electrically connected to the substrate through at least one of the conductive vias. A plurality of photo diode sensors are formed adjacent to the interconnect structure. Each photo diode sensor is surrounded by at least one of the conductive guard rings. Each photo diode sensor includes a pixel electrode. The pixel electrode is electrically connected to the substrate through a corresponding conductive via. An I-layer is formed adjacent to the pixel electrode. The array of active pixel sensors further includes a transparent conductive layer formed adjacent to the photo diode sensors.

Abstract: An image pixel sensor array. The image pixel sensor array includes a substrate. An interconnect structure is formed adjacent to the substrate. A plurality of image pixel sensors are formed adjacent to the interconnect structure. Each image pixel sensor includes a pixel electrode, and an I-layer formed adjacent to the pixel electrode. The I-layer includes a first surface adjacent to the pixel electrode, and a second surface opposite the first surface. The first surface includes a first surface area which is less than a second surface area of the second surface. The image pixel sensor array further includes an insulating material between each image pixel sensor, and a transparent electrode formed over the image pixel sensors. The transparent electrode electrically connects the image pixel sensors and the interconnect structure.

Abstract: An active pixel sensor. The active pixel sensor includes a substrate, an interconnect structure adjacent to the substrate, and at least one photo sensor adjacent to the interconnect structure. At least one photo sensor is formed adjacent to the interconnect structure. Each photo sensor includes a pixel electrode which includes a patterned doped semiconductor layer. An I-layer is formed adjacent to the patterned doped semiconductor layer. A transparent electrode is formed adjacent to the I-layer. A method of forming the active pixel sensor includes forming an interconnect structure over a substrate. Next, a doped semiconductor layer is deposited over the interconnect structure. The doped semiconductor layer is etched forming pixel electrode. An I-layer is deposited over the pixel electrodes. Finally, a transparent conductive layer is deposited over the I-layer.

Abstract: A color detection active pixel sensor. The color detection active pixel sensor includes a substrate. A diode is electrically connected to a first doped region of the substrate. The diode conducts charge when the diode receives photons having a first range of wavelengths. The substrate includes a second doped region. The second doped region conducts charge when receiving photons having a second range of wavelengths. The photons having the second range of wavelengths passing through the diode substantially undetected by the diode. The substrate can include a doped well within the substrate. The doped well conducts charge when receiving photons having a third range of wavelengths. The photons having the third range of wavelengths pass through the diode substantially undetected by the diode.

Abstract: An integrated circuit sensor structure. The integrated circuit sensor structure includes a substrate which includes electronic circuitry. An interconnect structure is adjacent to the substrate. The interconnect structure includes conductive interconnect vias which pass through the interconnect structure. A dielectric layer is adjacent to the interconnect structure. The dielectric layer includes a planar surface, and conductive dielectric vias which pass through the dielectric layer and are electrically connected to the interconnect vias. The dielectric layer further includes an interlayer planarization dielectric layer adjacent to the interconnect structure, and a passivating layer adjacent to the interlayer planarization dielectric layer. The integrated circuit sensor structure further includes sensors adjacent to the dielectric layer. The interconnect vias and the dielectric vias electrically connect the electronic circuitry to the sensors.

Abstract: An active pixel sensor. The active pixel sensor includes a substrate, an interconnect structure adjacent to the substrate, and at least one photo sensor adjacent to the interconnect structure. Each photo sensor includes an individual pixel electrode. An I-layer is formed over all of the pixel electrodes. A transparent electrode is formed over the I-layer. An inner surface of the transparent electrode is electrically connected to the I-layer and the interconnect structure.

Abstract: A dual-inlaid damascene contact having a polished surface for directly communicating an electrically conductive layer to a semiconductor layer. A dielectric layer is formed on the electrically conductive layer. A dual-inlaid cavity is formed by etching a via cavity and a contact cavity into the dielectric layer. A damascene contact is formed by depositing tungsten into the dual-inlaid cavity. Chemical-mechanical polishing is used to planarize and smooth a surface of the damascene contact until the surface is coplanar with the dielectric layer. A semiconductor layer is then deposited on the damascene contact. The semiconductor layer can be the node of an amorphous silicon P-I-N photodiode. Electrical interconnection between the node of the photodiode and the electrically conductive layer is accomplished without using an intermediate electrode, and the smooth damascene contact improves surface adhesion, reduces contact resistance, and provides a discrete connection to the semiconductor layer.