Abstract: A dual bit ROM multilayered structure with improved write and erase functions and a method of manufacturing is disclosed. The structure includes a pair of floating gates at the middle or nitride layer to better define the two locations of electrons representing the dual data bits collected in the middle layer.

Abstract: A novel method of forming a bond pad of a semiconductor device and a novel bond pad structure. Two passivation layers are used to form bond pads of a semiconductor device. A portion of the second passivation layer resides between adjacent bond pads, preventing shorting of the bond pads during subsequent wire bonding processes or flip-chip packaging processes.

Abstract: A novel method of forming a bond pad of a semiconductor device and a novel bond pad structure. Two passivation layers are used to form bond pads of a semiconductor device. A portion of the second passivation layer resides between adjacent bond pads, preventing shorting of the bond pads during subsequent wire bonding processes or flip-chip packaging processes.

Abstract: A novel method of forming a bond pad of a semiconductor device and a novel bond pad structure. Two passivation layers are used to form bond pads of a semiconductor device. A portion of the second passivation layer resides between adjacent bond pads, preventing shorting of the bond pads during subsequent wire bonding processes or flip-chip packaging processes.

Abstract: The present invention relates to an inorganic intercalating nano-catalyst with high activity for the copolymerization of carbon dioxide and epoxide. Said catalyst was prepared by intercalating zinc dicarboxylate into layered silicate. The zinc dicarboxylates were synthesized from zinc oxide and dicarboxylic acids. The silicate was activated at 600-1000° C. in a muffle furnace for a period 2˜10 h prior to intercalation. Zinc dicarboxylates were dissolved in strong polar solvents under pH value from 1.0 to 4.0. Calcinated acidic silicate was introduced into the reaction system to perform the intercalation 30˜120 minutes at the temperature from room temperature to 80° C. The crystal of the intercalating nano-catalysts was improved by refluxing in weak polar solvent followed by removing the solvent.

Abstract: A voltage-variable capacitor uses the channel-to-substrate junction from a gated diode formed from a metal-oxide-semiconductor transistor. The transistor gate has at least two contacts that are biased to different voltages. The gate acts as a resistor with current flowing from an upper gate contact to a lower gate contact. The gate-to-source voltage varies as a function of the position. A critical voltage is where the gate-to-source voltage is equal to the transistor threshold. A portion of the gate that has gate voltages above the critical voltage has an inversion layer or conducting channel under the gate. Another portion of the gate has gate voltages below the critical voltage, and thus no channel forms. By varying either the gate voltages or the source voltage, the area of the gate that has a channel under it is varied, varying the channel-to-substrate capacitance. Separate gate arms reduce bias current.

Abstract: A semiconductor isolation structure. The semiconductor isolation structure includes a substrate. A first device and a second device are formed within the substrate. An isolation region is formed within the substrate between the first device and the second device. The isolation region includes a deep region which extends into the substrate. The deep region includes a deep region cross-sectional area. A shallow region extends to the surface of the substrate. The shallow region includes a shallow region cross-sectional area. The deep region cross-sectional area is greater than the shallow region cross-sectional area. For an alternate embodiment, the deep region includes an oxide and the shallow region includes a protective wall. The protective wall can be formed from an oxide and a nitride.

Abstract: An image sensor. The image sensor array includes a substrate. An interconnect structure is formed adjacent to the substrate. An amorphous silicon electrode layer is adjacent to the interconnect structure. The amorphous silicon electrode layer includes electrode ion implantation regions between pixel electrode regions. The pixel electrode regions define cathodes of an array of image sensors. The electrode ion implantation regions provide physical isolation between the pixel electrode regions. The cathodes are electrically connected to the interconnect structure. An amorphous silicon I-layer is adjacent to the amorphous silicon electrode layer. The amorphous silicon I-layer forms an inner layer of each of the image sensors. A transparent electrode layer is formed adjacent to the image sensors. An inner surface of the transparent electrode is electrically connected to anodes of the image sensors and the interconnect structure.

Abstract: A voltage-variable capacitor uses the channel-to-substrate junction from a gated diode formed from a metal-oxide-semiconductor transistor. The transistor gate has at least two contacts that are biased to different voltages. The gate acts as a resistor with current flowing from an upper gate contact to a lower gate contact. The gate-to-source voltage varies as a function of the position. A critical voltage is where the gate-to-source voltage is equal to the transistor threshold. A portion of the gate that has gate voltages above the critical voltage has an inversion layer or conducting channel under the gate. Another portion of the gate has gate voltages below the critical voltage, and thus no channel forms. By varying either the gate voltages or the source voltage, the area of the gate that has a channel under it is varied, varying the channel-to-substrate capacitance. Separate gate arms reduce bias current.

Abstract: An array of image sensors that includes ion implantation regions that provide physical isolation between the pixel electrode regions. The physical isolation reduces coupling and cross-talk between the image sensors. The array of isolated image sensors can be formed by a simple fabrication process.

Abstract: An image sensor. The image sensor array includes a substrate. An interconnect structure is formed adjacent to the substrate. An amorphous silicon electrode layer is adjacent to the interconnect structure. The amorphous silicon electrode layer includes electrode ion implantation regions between pixel electrode regions. The pixel electrode regions define cathodes of an array of image sensors. The electrode ion implantation regions provide physical isolation between the pixel electrode regions. The cathodes are electrically connected to the interconnect structure. An amorphous silicon I-layer is adjacent to the amorphous silicon electrode layer. The amorphous silicon I-layer forms an inner layer of each of the image sensors. A transparent electrode layer is formed adjacent to the image sensors. An inner surface of the transparent electrode is electrically connected to anodes of the image sensors and the interconnect structure.

Abstract: An image sensor array. The image sensor array includes a substrate. An array of photo diode sensors are electrically interconnected to the substrate. The photo diode sensors conduct charge at a rate proportional to the intensity of light received by the photo diode sensors. A ring of guard diodes are located around the periphery of the array of photo diode sensors. Each guard diode has a guard diode anode connected to a predetermined guard anode voltage and a guard diode cathode connected to a static guard cathode voltage.

Abstract: A voltage-variable capacitor is constructed from a metal-oxide-semiconductor transistor. The transistor source has at least two contacts that are biased to different voltages. The source acts as a resistor with current flowing from an upper source contact to a lower source contact. The gate-to-source voltage varies as a function of the position along the source-gate edge. A critical voltage is where the gate-to-source voltage is equal to the transistor threshold. A portion of the source has source voltages above the critical voltage and no conducting channel forms under the gate. Another portion of the source has source voltages below the critical voltage, and thus a conducting channel forms under the gate for this portion of the capacitor. By varying either the gate voltage or the source voltages, the area of the gate that has a channel under it is varied, varying the capacitance. Separate source islands eliminate source current.

Abstract: An array of light-sensitive sensors utilizes bipolar phototransistors that are formed of multiple amorphous semiconductor layers, such as silicon. In the preferred embodiment, the bipolar transistors are open base devices. In this preferred embodiment, the holes that are generated by reception of incoming photons to a particular open base phototransistor provide current injection to the base region of the phototransistor. The collector region is preferably an intrinsic amorphous silicon layer. The phototransistors may be operated in either an integrating mode in which bipolar current is integrated or a static mode in which a light-responsive voltage is monitored.

Abstract: An array of active pixel sensors includes a substrate. An interconnect structure is formed adjacent to the substrate. The interconnect structure includes a plurality of conductive vias. A plurality of photo sensors are formed adjacent to the interconnect structure. Each photo sensor includes a pixel electrode. Each pixel electrode is electrically connected to the substrate through a corresponding conductive yet. A I-layer is formed over each of the pixel electrodes. The array of active pixel sensors further includes a conductive mesh formed adjacent to the photo sensors. An inner surface of the conductive mesh is electrically and physically connected to the photo sensors, and electrically connected to the substrate through a conductive via. The conductive mesh providing light shielding between photo sensors thereby reducing cross-talk between the photo sensors. The conductive mesh includes apertures that align with at least one of the pixel electrodes of the photo sensors.

Abstract: A structure and a method for providing structural stability at an interface between two poorly adhering layers in a semiconductor device involve providing anchoring channels in one of the poorly adhering layers through which the other poorly adhering layer can be anchored to a third layer. Specifically, the structure and method are applicable to a three-layer stack having a top layer of amorphous silicon, a middle layer of titanium nitride, and a bottom layer of oxide. In order to reduce susceptibility to delamination between the amorphous silicon layer and the titanium nitride layer, the anchoring channels are created in the titanium nitride layer to allow the amorphous silicon to attach to the oxide layer. Because the amorphous silicon layer and the oxide layer exhibit good adhesion between each other, delamination between the amorphous silicon layer and the titanium nitride layer is minimized.

Abstract: A self-aligned metal electrode sensor structure. The self-aligned metal electrode sensor structure includes a substrate which includes electronic circuitry. An interconnect structure is formed adjacent to the substrate. The interconnect structure includes conductive interconnect vias which pass through the interconnect structure. A sensor is formed adjacent to the interconnect structure. The sensor includes a pixel metallization section and a doped layer electrode. The pixel metallization section is electrically connected to the interconnect via. The pixel metallization section includes an outer surface which is substantially planar. The doped layer electrode includes an inner surface adjacent to the outer surface of the pixel metallization section. The entire inner surface of the doped layer electrode is substantially planar. A transparent conductive layer is formed adjacent to the sensor. The interconnect via and the transparent conductive layer electrically connect the electronic circuitry to the sensor.

Abstract: A self-aligned metal electrode sensor structure. The self-aligned metal electrode sensor structure includes a substrate which includes electronic circuitry. An interconnect structure is formed adjacent to the substrate. The interconnect structure includes conductive interconnect vias which pass through the interconnect structure. A sensor is formed adjacent to the interconnect structure. The sensor includes a pixel metallization section and a doped layer electrode. The pixel metallization section is electrically connected to the interconnect via. The pixel metallization section includes an outer surface which is substantially planar. The doped layer electrode includes an inner surface adjacent to the outer surface of the pixel metallization section. The entire inner surface of the doped layer electrode is substantially planar. A transparent conductive layer is formed adjacent to the sensor. The interconnect via and the transparent conductive layer electrically connect the electronic circuitry to the sensor.

Abstract: A highly-efficient thermal inkjet printhead. The printhead includes a primary layer of polycrystalline silicon (preferably doped) having at least one portion thereof which functions as an ink expulsion resistor. Positioned over and above the primary layer is a secondary layer of material having at least one section produced from a selected metal silicide compound and at least another section fabricated from undoped polycrystalline silicon. The metal silicide-containing section functions as an interconnect structure and is operatively connected to the resistor in the primary layer (which is positioned beneath the secondary layer). The undoped polycrystalline silicon section is at least partially aligned over and above the resistor. As a result, the resistor is “buried” beneath the secondary layer and the various portions thereof. This system provides improved reliability, greater dimensional simplicity, optimized electrical/thermal properties, and superior versatility.

Abstract: A highly-efficient thermal inkjet printhead. The printhead includes at least one doped polycrystalline silicon resistor which communicates with an external signal source using a unique interconnection system. Specifically, a primary layer of electrically conductive material (optimally a metal silicide) is connected to the resistor. An additional layer of electrically conductive material is attached to and above the primary layer. The additional layer terminates at a position which is spaced outwardly and apart from the resistor to form a gap therebetween. However, the underlying primary layer electrically links the additional layer to the resistor. Alternatively, a dielectric layer is attached to and above the primary layer, with the additional layer being secured to the dielectric layer. At least one electrically conductive contact member is provided within the dielectric layer to link the primary and additional layers.