Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a conductive structure arranged within a substrate or a first dielectric layer. A first barrier layer is arranged on outermost sidewalls and a bottom surface of the conductive structure. A second barrier layer is arranged on outer surfaces of the first barrier layer. The second barrier layer separates the first barrier layer from the substrate or the first dielectric layer. A second dielectric layer is arranged over the substrate or the first dielectric layer. A via structure extends through the second dielectric layer, is arranged directly over topmost surfaces of the first and second barrier layers, and is electrically coupled to the conductive structure through the first and second barrier layers.

Abstract: A glue dispensing device comprises a base, a pressure control unit, a quantitative glue supply unit and a glue dispensing needle. The base comprises a pressure control chamber and a glue tube body, the pressure control chamber is located inside the base, the glue tube body extends from one end of the base to the other end, and the glue tube body penetrates the pressure control chamber. The pressure control unit is coupled to the pressure control chamber. The quantitative glue supply unit is disposed at one end of the base body and is coupled to the glue tube body. The glue dispensing needle is disposed at the other end of the base and is coupled to the glue tube body. The glue dispensing device uses the pressure change of the pressure control chamber to deform the glue tube body, thereby achieving quantitative glue dispensing effect with accuracy and stability. In addition, a glue dispensing method is also disclosed.

Abstract: A jetting valve with two stage calibrating structures is disclosed, the jetting valve includes: a casing having an accommodating space; a piezoelectric actuating unit disposed on one side of the accommodating space; a spraying unit disposed on the other side of the accommodating space; a displacement amplifying element is arranged at the bottom of the accommodating space and leans against on the spraying unit, the bottom end of the piezoelectric driving unit is in contact with the displacement amplifying element; a sensing unit is arranged on the periphery of the displacement amplifying element to sense the movement of the spraying unit; a control unit, connected to the sensing unit and the piezoelectric actuating unit, adjusting the voltage supplied to the piezoelectric driving unit according to data obtained by the sensing unit; and a liquid supply unit connected to the spraying unit.

Abstract: A reciprocating glue dispenser dispensing switch includes a switching device main body, a needle holding base, a sliding wear-resistant plate, and a driving device. The switching device main body is equipped with a double liquid inlet, the needle holding base is equipped with a mixed glue outlet, the sliding wear-resistant plate is installed between the switching device main body and the needle holding base, and the sliding wear-resistant plate is equipped with a sliding wear-resistant plate opening. The driving device is utilized to move the sliding wear-resistant plate. A mixed double-liquid glue passes through the double liquid inlet, the sliding wear-resistant plate opening and the glue outlet to dispense a mixed double-liquid glue while the double liquid inlet, the sliding wear-resistant plate opening and the glue outlet are overlapped.

Abstract: Provided in the present invention is the use of a proprotein convertase subtilisin/kexin type 9 (PCSK9) inhibitor in a product for treating multiple diseases. The PCSK9 inhibitor is a PCSK9 small molecule compound, or a PCSK9 interfering RNA, or a PCSK9 monoclonal antibody, or a PCSK9 mimetic peptide, or a PCSK9 mimetic antibody protein, or a PCSK9 antisense oligonucleotide or a PCSK9 vaccine.

Abstract: A motor current protecting circuit is provided. A voltage calculating circuit determines whether or not each of low-side switches is fully turned on and then determines whether or not a voltage difference between a first terminal and a second terminal of each of the low-side switches being fully turned on is larger than or equal to a zero value. The voltage calculating circuit adds up the voltage differences each of which is larger than or equal to the zero value to output a voltage signal. A control circuit controls a driver circuit to switch the low-side switches and high-side switches according to the voltage signal.

Abstract: A capacitor structure for a power semiconductor device includes a semiconductor substrate, an isolation insulating layer having a ring-shape and including an outer periphery and an inner periphery defining an opening region, a first electrode disposed on the isolation insulating layer, a dielectric layer disposed on the first electrode, and a second electrode disposed on the dielectric layer.

Abstract: A shear test is conducted on an interconnect bond formed on a surface of an electronic device by first determining a profile of the surface, and based on the determined profile, determining a shearing path which is at a substantially constant distance from the profile of the surface for a shear test tool to conduct the shear test on the interconnect bond. The shear test tool is then guided to move along the determined shearing path to measure a shear force of the interconnect bond.

Abstract: This application discloses example data sending methods and apparatuses, and an example FlexE switching system. In one example, when slice packets received include a SOP flag and an EOP flag of a same data packet, immediately data packet slices is restored in the slice packets to a FlexE data stream and the FlexE data stream is sent, or the data packet slices are restored in the slice packets to the FlexE data stream and the FlexE data stream is sent when a latency is greater than or equal to a first present duration. When the slice packets received include the SOP flag but do not include the EOP flag of a data packet, the data packet slices are restored in the slice packets and the FlexE data stream is sent when the latency reaches a second preset duration. The first preset duration is less than the second preset duration.

Abstract: Systems and methods are provided for trapping and electrically monitoring molecules in a nanopore sensor. The nanopore sensor comprises a support structure with a first and a second fluidic chamber, at least one nanopore fluidically connected to the two chambers, and a protein shuttle. The protein shuttle comprises an electrically charged protein molecule, such as Avidin. The nanopore can be a Clytosolin A. A method can comprise applying a voltage across the nanopores to draw protein shuttles towards the nanopores. The ionic current through each or all of the nanopores can be concurrently measured. Based on the measured ionic current, blockage events can be detected. Each blockage event indicates a capture of a protein shuttle by at least one nanopore. Each blockage event can be detected through a change of the total ionic current flow or a change in the ionic current flow for a particular nanopore.

Abstract: A glue dispensing system and the glue supplying method thereof are disclosed. The glue dispensing system uses at least one feed tank to provide or supply the glue to a glue dispensing needle cylinder. Thus, the glue dispensing needle cylinder does not need to be replaced or the frequency of replacing the glue dispensing needle cylinder can be decreased in order to save more time, reduce manpower waste and decrease the cost.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a conductive structure arranged within a substrate or a first dielectric layer. A first barrier layer is arranged on outermost sidewalls and a bottom surface of the conductive structure. A second barrier layer is arranged on outer surfaces of the first barrier layer. The second barrier layer separates the first barrier layer from the substrate or the first dielectric layer. A second dielectric layer is arranged over the substrate or the first dielectric layer. A via structure extends through the second dielectric layer, is arranged directly over topmost surfaces of the first and second barrier layers, and is electrically coupled to the conductive structure through the first and second barrier layers.

Abstract: A graphical ultrasonic module and driver assistance system are provided. The graphical ultrasonic module includes an ultrasonic sensor array and an ultrasonic transmitter array. The ultrasonic sensor array includes three or more ultrasonic sensors, and the ultrasonic sensors form a virtual plane. The ultrasonic transmitter array includes a plurality of ultrasonic transmitters. The geometric center of the ultrasonic transmitter array is substantially the same as the geometric center of the ultrasonic sensor array.

Abstract: A wet etching chemistry to selectively remove a polymer residue on an opening embedded in a low-k dielectric layer and an underlying stop layer in a process of forming an interconnect structure is provided. The wet etching chemistry includes: two type of organic solvents, wherein a concentration of the two type of organic solvents is greater than or equal to 70%; an Alkali source amine, at least comprising a tertiary amine; an inhibitor; and water. In some embodiment, the wet etching chemistry is free of a peroxide to avoid damage to the WdC hard mask.

Abstract: An automatic generation system of a training image and a method thereof are provided. The disclosure generates a training image and records the target category and the target position. The disclosure adds the target image to the container image as a candidate image, calculates a reliability of the candidate image, and repeatedly executes the process until the reliability of the candidate image meets a threshold condition for generating the training image. The disclosure is able to generate the training images automatically, and the recognition difficulty of the training image is adjustable by the user, so as to be suitable for customized recognition training.

Abstract: A mass transferring system and the method thereof are provided. The system includes two platforms and a plurality of picking and placing units. When the mass transferring process is performed for one of the substrates, the replacing process and the aligning process are simultaneously executed for another one of the substrates, such that the mass transferring process and the replacing process can be performed at the same time. Compared with the conventional mass transferring processes, the efficiency of the mass transferring system and the method thereof according to the present invention can be increased by 90%.

Abstract: A rotation locking system of a motor of a fan is provided. A closed-loop control circuit outputs an initial duty cycle signal according to a current rotational speed and a target rotational speed. A driver circuit outputs a driving signal to the motor to drive the motor to rotate according to the initial duty cycle signal. A lookup table arithmetic circuit looks up, from a lookup table, two reference duty cycles correspond to two reference rotational speeds that are respectively equal to the current rotational speed and the target rotational speed. The lookup table arithmetic circuit calculates a difference between the two reference duty cycles. A speed feedback control circuit compensates the initial duty cycle signal according to the difference to output a final duty cycle signal to the driver circuit. The driver circuit drives the motor to rotate according to the final duty cycle signal.

Abstract: An integrated circuit (IC) including a first ring oscillator (RO) including a first set of cascaded stages, wherein each of the first set of cascaded stages comprises a first logic inverter, including: a first set of field effect transistors (FETs) coupled in parallel between a first voltage rail and a first intermediate node, wherein the first set of FETs include a set of gates coupled to an input of the first logic inverter; and a second set of FETs coupled in series between the first intermediate node and a second voltage rail, wherein the second set of FETs includes at least a first FET including a gate coupled to the input of the first logic inverter, and at least a second FET that is diode-connected in accordance with a first mode of operation.

Abstract: A package structure of an embedded power module includes a top insulation layer, a top metal pattern layer, a solder layer, a device layer, a bottom metal pattern layer and a bottom insulation layer sequentially arranged from top to bottom. The device layer includes at least two MOSFET bare dies and several metal connection blocks, and is filled with insulation filler to isolate the MOSFET bare dies and the metal connection blocks from each other. The drain electrodes of the bare dies are connected with the top metal pattern layer through the solder layer, and the source electrodes and the gate electrodes of the bare dies are electrically connected to the bottom metal pattern layer, respectively. The upper and lower surfaces of the metal connection blocks are electrically connected to the top metal pattern layer and the bottom metal pattern layer, respectively.

Abstract: A series circuit and a computing device include a power supply terminal for providing voltage for a plurality of chips disposed on the computing device; a ground terminal disposed at one end of each of the plurality of chips relative to the power supply terminal; and a first connection line for separately connecting a first predetermined number of chips of the plurality of chips in series, wherein a communication line is connected between adjacent chips of the first predetermined number of chips, a portion of the communication line is connected to a target connection point, which is disposed on the first connection line and adapted to the adjacent chips, via a third connection line, and the voltage at the target connection point is greater than or equal to the minimum voltage required for communication between the adjacent chips.