Patents by Inventor Min-Cheol Shin

Min-Cheol Shin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6037198
    Abstract: The present invention is to fabricate SOI wafer whose the silicon layer is very uniform and the impurity concentration is low. The insulating layer, that is, a composite layer of SiO2 and silicon, is grown on oxide substrate by means of a molecular beam epitaxy fabricating method using silicon as an original material in the oxygen atmosphere. The composite layer of the oxide and silicon is grown according to gradual decreasing the pressure of oxygen atmosphere. A top silicon layer of uniform thickness is grown by means of a molecular beam epitaxy fabricating method using only silicon material consecutively on the composite layer.
    Type: Grant
    Filed: August 25, 1998
    Date of Patent: March 14, 2000
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Kyoung Wan Park, Seong Jae Lee, Moon Ho Park, Min Cheol Shin, Sang Chul Oh
  • Patent number: 5994714
    Abstract: The present invention discloses a technique for applying diffraction characteristic of electrons to a two-dimensional electronic device to manufacture multi-functional transistor having various ON/OFF states. A quantum diffraction transistor according to the present invention is capable of adjusting the amplitude of drain current and having various ON/OFF states utilizing diffraction characteristic of electrons by interposing a reflection-type diffraction grating in an electron path. The inventive multi-functional quantum diffraction transistor uses a two dimensional electron gas in formed at a different species junction in a semiconductor heterostructure, and has a bent electron path between the source electrode and the drain electrode with a reflection-type diffraction grating. The quantum diffraction effect of the electrons is used for the control of the diffracted drain current.
    Type: Grant
    Filed: September 17, 1997
    Date of Patent: November 30, 1999
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Kyoung Wan Park, Seong Jae Lee, Min Cheol Shin
  • Patent number: 5940696
    Abstract: The present invention discloses a technique for applying diffraction characteristics of electrons to a two-dimensional electronic device to manufacture multi-functional transistor having various ON/OFF states. Method of manufacturing a quantum diffraction transistor according to the present invention is capable of adjusting the amplitude of drain current and having various ON/OFF states utilizing diffraction characteristics of electrons by interposing a reflection-type diffraction grating in a bent electron path. In the inventive multi-functional quantum diffraction transistor using a two dimensional electron gas in quantum well structure formed at a different species junction in a heterostructure semiconductor device and having a bent electron path between the source electrode and the drain electrode with a reflection-type diffraction grating, the quantum diffraction effect of the electrons is used for the control of the diffracted drain current.
    Type: Grant
    Filed: September 17, 1997
    Date of Patent: August 17, 1999
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Kyoung Wan Park, Seong Jae Lee, Min Cheol Shin
  • Patent number: 5883419
    Abstract: A transistor in accordance with the invention comprises an ultra-thin Mo--C film functioning as a channel for an electron flow with two ends of the thin metal film functioning as source and drain terminals of the transistor, respectively; a piezoelectric film formed on the Mo--C film, for producing a force in accordance with an applied electric field provided by a gate voltage; and an electrode film formed on the piezoelectric film functioning as a gate of the transistor to which the gate voltage is applied to produce the applied electric field; and wherein a resistance of the Mo--C film between the source and drain terminals changes in accordance with the force produced in response to the applied gate voltage. This transistor can be used as an element of the three dimensional integrated circuit with a laminated structure.
    Type: Grant
    Filed: May 1, 1997
    Date of Patent: March 16, 1999
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Seong-Jae Lee, Kyoung-Wan Park, Min-Cheol Shin
  • Patent number: 5880484
    Abstract: A lateral resonant tunneling transistor having two non-symmetric quantum dots is disclosed. When a negative voltage is supplied to each plurality of thin split gates, two non-symmetric quantum dots are formed owing to the formation of the potential barrier. Thus when a forward bias voltage is applied, the resonant tunneling phenomena occur twice successively. Through these two successive resonant tunneling phenomena and by lowering the height of the third potential barrier 6a, the resonant tunneling current can be maximized.
    Type: Grant
    Filed: September 4, 1996
    Date of Patent: March 9, 1999
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Kyoung-Wan Park, Seong-Jae Lee, Min-Cheol Shin
  • Patent number: 5872372
    Abstract: A thin film transistor is disclosed comprising a piezoelectric film formed on a piezoresistive body of an ultra thin film and a gate electrode formed on the piezoelectric film. Due to the force generated from the piezoelectric film by an electric field generated according to the strength of a voltage applied to the gate electrode, a pressure is applied on the piezoresistive body to vary the resistance of the piezoresistive body. Thus, the quantity of current that flows from a source terminal through the piezoresistive channel to a drain terminal can be controlled. Since the piezoresistive body can be formed on a plane, a thin film transistor with a three-dimensional structure can be manufactured.
    Type: Grant
    Filed: September 11, 1996
    Date of Patent: February 16, 1999
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Seong-Jae Lee, Kyoung-Wan Park, Min-Cheol Shin
  • Patent number: 5760675
    Abstract: Disclosed is the method of producing a piezo-device utilizing an ultra-thin Mo-C film as a piezoresistive material for a general class of improved piezo-device with the high sensitivity and the weak temperature dependence.
    Type: Grant
    Filed: September 19, 1996
    Date of Patent: June 2, 1998
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Seong-Jae Lee, Kyoung-Wan Park, Min-Cheol Shin
  • Patent number: 5519232
    Abstract: A quantum interference device comprises a semi-insulating GaAs substrate; GaAs and AlGaAs layers sequentially formed with high purity on the substrate; a two-dimensional electron gas layer formed in the GaAs layer and serving as a channel; source/drain regions formed on the semi-insulating GaAs substrate and at both ends of a laminated portion composed of the GaAs/AlGaAs layers; and a gate formed on the AlGaAs layer and having a periodic structure wherein the length thereof varies in a periodic manner in a transverse direction. In the device, the electron gas layer formed in the GaAs layer is used as an electron path, and the phases of electrons passing along different electron paths are caused to interfere with each other by the gate, thereby causing the current of a drain therein to be maximized or minimized. The transconductance can be significantly increased.
    Type: Grant
    Filed: November 30, 1994
    Date of Patent: May 21, 1996
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Kyoung-Wan Park, Seong-Jae Lee, Min-Cheol Shin