Abstract: Compositions and methods for selectively removing unreacted metal material (e.g., unreacted nickel) relative to metal germanide (e.g., NiGe), metal-III-V materials, and germanium from microelectronic devices having same thereon. The compositions are substantially compatible with other materials present on the microelectronic device such as low-k dielectrics and silicon nitride.

Abstract: Liquid compositions useful for the cleaning of residue and contaminants from a III-V microelectronic device material, such as InGaAs, without substantially removing the III-V material. The liquid compositions are improvements of the SC1 and SC2 formulations.

Abstract: An electronic device includes a computing module and a display module. The computing module executes a first operating system. When the display module is in a connection area with the computing module, the display module displays an image of the first operating system. When the display module is outside the connection area, the display module executes a second operating system, and displays an image of the second operating system.

Abstract: A method for increasing the removal rate of a photoresist layer is provided. The method includes performing a pre-treatment of a substrate, such as a plasma process, before forming the photoresist layer. The method can be applied to the fabrication of semiconductor devices for increasing the removal rate of the photoresist layer.

Abstract: A stacked structure for patterning a material layer to form an opening pattern with a predetermined opening width in the layer is provided. The stacked structure includes an underlayer, a silicon rich organic layer, and a photoresist layer. The underlayer is on the material layer. The silicon rich organic layer is between the underlayer and the photoresist layer. The thickness of the photoresist layer is smaller than that of the underlayer and larger than two times of the thickness of the silicon rich organic layer. The thickness of the underlayer is smaller than three times of the predetermined opening width.

Abstract: A stacked structure for patterning a material layer to form an opening pattern with a predetermined opening width in the layer is provided. The stacked structure includes an underlayer, a silicon rich organic layer, and a photoresist layer. The underlayer is on the material layer. The silicon rich organic layer is between the underlayer and the photoresist layer. The thickness of the photoresist layer is smaller than that of the underlayer and larger than two times of the thickness of the silicon rich organic layer. The thickness of the underlayer is smaller than three times of the predetermined opening width.

Abstract: A patterning method is provided. In the patterning method, a film is formed on a substrate and a pre-layer information is measured. Next, an etching process is performed to etch the film. The etching process includes a main etching step, an etching endpoint detection step, an extension etching step and an over etching step. An extension etching time for performing the extension etching step is set within 10 seconds based on a predetermined correlation between an extension etching time and the pre-layer information, so as to achieve a required film profile.

Abstract: A method of forming a pattern for a semiconductor device, in which, two hard masks are included between an upper spin-on glass (SOG) layer and a lower etching target layer. The SOG layer is etched twice through two different patterned photoresists respectively to form a fine pattern in the SOG layer. Subsequently, an upper hard mask is etched by utilizing the patterned SOG layer as an etching mask so the upper patterned hard mask can have a fine pattern with a sound shape and enough thickness. A lower hard mask and the etching target layer are thereafter etched by utilizing the upper patterned hard mask as an etching mask, so portions of the etching target layer that are covered by the two hard masks can be well protected from the etching processes.

Abstract: A method of forming a pattern for a semiconductor device, in which, two hard masks are included between an upper spin-on glass (SOG) layer and a lower etching target layer. The SOG layer is etched twice through two different patterned photoresists respectively to form a fine pattern in the SOG layer. Subsequently, an upper hard mask is etched by utilizing the patterned SOG layer as an etching mask so the upper patterned hard mask can have a fine pattern with a sound shape and enough thickness. A lower hard mask and the etching target layer are thereafter etched by utilizing the upper patterned hard mask as an etching mask, so portions of the etching target layer that are covered by the two hard masks can be well protected from the etching processes.

Abstract: A method of forming a metal-oxide-semiconductor (MOS) device is provided. The method includes the following steps. First, a conductive type MOS transistor is formed on a substrate. Then, a first etching stop layer is formed over the substrate to cover conformably the conductive type MOS transistor. Thereafter, a stress layer is formed over the first etching stop layer. Then, a second etching stop layer is formed over the stress layer.

Abstract: A method of trimming hard mask is provided. The method includes providing a substrate, a hard mask layer, and a tri-layer stack on the substrate. The tri-layer stack includes a top photo resist layer, a silicon photo resist layer, and a bottom photo resist layer. The top photo resist layer, the silicon photo resist layer, the bottom photo resist layer, and the hard mask layer are patterned sequentially. A trimming process is performed on the hard mask layer. The bottom photo resist layer of the present invention is thinner and loses some height in the etching process, so the bottom photo resist layer will not collapse.

Abstract: A stack structure for forming a gate of a MOS transistor includes a substrate including a plurality of shallow trench isolations therein; a dielectric layer, a conductive layer and a hard mask layer formed on the substrate in sequence; and a tri-layer stack comprising a top photo resist layer, a silicon-containing photo resist layer and a bottom anti-reflective coating (BARC) on the hard mask layer, wherein the silicon-containing photo resist layer comprises 10-30% silicon and the hard mask layer has a high etching selectivity ratio to the conductive layer.

Abstract: A method for increasing the removal rate of a photoresist layer is provided. The method includes performing a pre-treatment of a substrate, such as a plasma process, before forming the photoresist layer. The method can be applied to the fabrication of semiconductor devices for increasing the removal rate of the photoresist layer.

Abstract: A method for increasing the removal rate of a photoresist layer used as an ion implant mask. The method includes performing a pre-treatment of a substrate, such as a plasma process, before forming the photoresist layer. The method can be applied to the fabrication of semiconductor devices for increasing the removal rate of the photoresist layer.

Abstract: A patterning method is provided. In the patterning method, a film is formed on a substrate and a pre-layer information is measured. Next, an etching process is performed to etch the film. The etching process includes a main etching step, an etching endpoint detection step, an extension etching step and an over etching step. An extension etching time for performing the extension etching step is set within 10 seconds based on a predetermined correlation between an extension etching time and the pre-layer information, so as to achieve a required film profile.

Abstract: A method of trimming hard mask is provided. The method includes providing a substrate, a hard mask layer, and a tri-layer stack on the substrate. The tri-layer stack includes a top photo resist layer, a silicon photo resist layer, and a bottom photo resist layer. The top photo resist layer, the silicon photo resist layer, the bottom photo resist layer, and the hard mask layer are patterned sequentially. A trimming process is performed on the hard mask layer. The bottom photo resist layer of the present invention is thinner and loses some height in the etching process, so the bottom photo resist layer will not collapse.

Abstract: A metal-oxide-semiconductor (MOS) transistor comprising a conductive type MOS transistor, a first etching stop layer, a stress layer and a second etching stop layer is provided. The conductive MOS transistor is disposed on a substrate. The first etching stop layer is covered conformably the conductive type MOS transistor. Furthermore, the stress layer is disposed on the first etching stop layer. The second etching stop layer is disposed on the stress layer.

Abstract: A patterning method is provided. The method includes the steps of firstly forming an underlying layer, a silicon rich organic layer, and a photoresist layer on the material layer in succession. The photoresist layer is patterned, and the silicon rich organic layer is etched using the photoresist layer as a mask. Then, an etching process is performed to pattern the underlying layer using the silicon rich organic layer as a mask. Reactive gases adopted in the etching process include a passivation gas, an etching gas, and a carrier gas. The passivation gas forms a passivation layer at side walls of the patterned underlying layer during the etching process. After that, the material layer is etched using the underlying layer as a mask to form an opening in material layer. Finally, the underlying layer is removed.

Abstract: A method of forming a metal-oxide-semiconductor (MOS) device is provided. The method includes the following steps. First, a conductive type MOS transistor is formed on a substrate. Then, a first etching stop layer is formed over the substrate to cover conformably the conductive type MOS transistor. Thereafter, a stress layer is formed over the first etching stop layer. Then, a second etching stop layer is formed over the stress layer.

Abstract: A stacked structure for patterning a material layer to form an opening pattern with a predetermined opening width in the layer is provided. The stacked structure includes an underlayer, a silicon rich organic layer, and a photoresist layer. The underlayer is on the material layer. The silicon rich organic layer is between the underlayer and the photoresist layer. The thickness of the photoresist layer is smaller than that of the underlayer and larger than two times of the thickness of the silicon rich organic layer. The thickness of the underlayer is smaller than three times of the predetermined opening width.