Abstract: The present disclosure provides a method of forming a semiconductor structure. The method includes providing a substrate including an isolation region, an active region adjacent to the isolation region, and a first top surface, wherein the isolation region includes an isolation trench filled with a dielectric material, and the active region includes a gate trench filled with a gate electrode material; forming a hard mask on the substrate; and performing an etching process to partially remove portions of the dielectric material and gate electrode material exposed by the hard mask to form a second top surface of the dielectric material and a third top surface of the gate electrode material, wherein the second top surface and the third top surface are substantially at the same level and are substantially lower than the first top surface.

Abstract: The present disclosure provides a method of forming a semiconductor structure. The method comprises providing a substrate comprising an isolation region, an active region adjacent to the isolation region, and a first top surface, wherein the isolation region includes an isolation trench filled with a dielectric material, and the active region includes a gate trench filled with a gate electrode material; forming a hard mask on the substrate; and performing an etching process to partially remove portions of the dielectric material and gate electrode material exposed by the hard mask to form a second top surface of the dielectric material and a third top surface of the gate electrode material, wherein the second top surface and the third top surface are substantially at the same level and are substantially lower than the first top surface.

Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes: forming a dummy via in a trench of a stacking structure with a bottom anti-reflection coated material, in which the stacking structure includes a low-k material layer and a cap layer, and the trench runs through the low-k material layer and the cap layer; and removing a portion of the dummy via by performing a first etching process and a second etching process, and in which the first etching process and the second etching process are performed such that a top surface of the dummy via is lower than a top surface of the low-k material layer and higher than a bottom surface of the low-k material layer.

Abstract: A method of manufacturing a semiconductor structure is provided by embodiments of this disclosure, and the method includes the following steps. An insulating area and an active area are formed in a substrate. A first word line trench is formed in the active are. A first dielectric layer is deposited in the first word line trench and on the active area and the insulating area. A second word line trench is formed through etching the first dielectric layer. Besides, the second word line trench is linear and extends through the insulating area and the active area of the substrate, and a portion of the first dielectric layer is remained in a bottom of the second word line trench. Then, a word line structure is formed in the second word line trench. Moreover, a semiconductor structure is provided in this disclosure.

Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes: filling a trench of a stacking structure with a bottom anti-reflection coated material to form a dummy via in the trench, in which the stacking structure includes a low-k material layer and a cap layer, and the trench runs through the low-k material layer and the cap layer; and etching the dummy via by performing a first etching process and a second etching process.

Abstract: The present disclosure provides a semiconductor structure having a fin structure. The semiconductor includes a substrate defined with an active region. A first gate structure is disposed in the active region and includes a dielectric material. A second gate structure is disposed in the active region and includes the dielectric material. A fin structure having a first top surface is arranged to alternate with the first gate structure and the second gate structure. The first gate structure has a second top surface and the second gate structure has a third top surface. The second top surface and the third top surface are lower than the first top surface.

Abstract: The present application provides a wiring structure, a semiconductor device having the wiring structure, and a method of manufacturing the semiconductor device. The wiring structure includes a substrate, a metallic layer above the substrate, at least one first conductive feature and at least one second conductive feature. The first and second conductive features are disposed between the substrate and the metallic layer; the first conductive feature has a first critical dimension, and the second conductive feature has a second critical dimension less than the first critical dimension. An effective resistance of the wiring structure can be adjusted by changing the critical dimensions of the first and second conductive features. The semiconductor device including the wiring structure and a method of manufacturing the semiconductor device are also provided.

Abstract: The present application provides a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a substrate and a wiring structure. The wiring structure includes at least one metal interconnect disposed on the substrate, at least one conductive feature disposed on the metal interconnect, and at least one diffusing barrier liner surrounding the conductive feature. The conductive feature has a head portion and a neck portion sandwiched between the metal interconnect and the head portion. The neck portion can have a first critical dimension, which gradually decreases at positions of increasing distance from the head portion.

Abstract: The present application provides a wiring structure, a semiconductor device having the wiring structure, and a method of manufacturing the semiconductor device. The wiring structure includes a substrate, a metallic layer above the substrate, at least one first conductive feature and at least one second conductive feature. The first and second conductive features are disposed between the substrate and the metallic layer; the first conductive feature has a first critical dimension, and the second conductive feature has a second critical dimension less than the first critical dimension. An effective resistance of the wiring structure can be adjusted by changing the critical dimensions of the first and second conductive features. The semiconductor device including the wiring structure and a method of manufacturing the semiconductor device are also provided.

Abstract: The present application provides a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a substrate and a wiring structure. The wiring structure includes at least one metal interconnect disposed on the substrate, at least one conductive feature disposed on the metal interconnect, and at least one diffusing barrier liner surrounding the conductive feature. The conductive feature has a head portion and a neck portion sandwiched between the metal interconnect and the head portion. The neck portion can have a first critical dimension, which gradually decreases at positions of increasing distance from the head portion.

Abstract: A method for preparing a semiconductor device is provided. The method includes forming a first dielectric layer over a semiconductor substrate, and forming a conductive contact penetrating through the first dielectric layer. The method also includes forming a lower landing pad over the conductive contact, and forming a second dielectric layer covering the lower landing pad. The method further includes etching the second dielectric layer to form a first opening exposing the lower landing pad, and forming an upper landing pad in the first opening. The lower landing pad and the upper landing pad form a T-shaped landing pad structure.

Abstract: A semiconductor device includes a first dielectric layer disposed over a semiconductor substrate, and a conductive contact penetrating through the first dielectric layer. The semiconductor device also includes a T-shaped landing pad structure disposed over and in direct contact with the conductive contact. The T-shaped landing pad structure includes a lower landing pad and an upper landing pad disposed over the lower landing pad, and a width of the upper landing pad is greater than a width of the lower landing pad. The semiconductor device further includes a capacitor disposed over and in direct contact with the T-shaped landing pad structure, and a second dielectric layer disposed over the first dielectric layer and surrounding the T-shaped landing pad structure and the capacitor.

Abstract: The present disclosure provides a method of forming a semiconductor structure. The method includes providing a substrate including an isolation region, an active region adjacent to the isolation region, and a first top surface, wherein the isolation region includes an isolation trench filled with a dielectric material, and the active region includes a gate trench filled with a gate electrode material; forming a hard mask on the substrate; and performing an etching process to partially remove portions of the dielectric material and gate electrode material exposed by the hard mask to form a second top surface of the dielectric material and a third top surface of the gate electrode material, wherein the second top surface and the third top surface are substantially at the same level and are substantially lower than the first top surface.

Abstract: A semiconductor device includes a first dielectric layer disposed over a semiconductor substrate, and a conductive contact penetrating through the first dielectric layer. The semiconductor device also includes a T-shaped landing pad structure disposed over and in direct contact with the conductive contact. The T-shaped landing pad structure includes a lower landing pad and an upper landing pad disposed over the lower landing pad, and a width of the upper landing pad is greater than a width of the lower landing pad. The semiconductor device further includes a capacitor disposed over and in direct contact with the T-shaped landing pad structure, and a second dielectric layer disposed over the first dielectric layer and surrounding the T-shaped landing pad structure and the capacitor.

Abstract: A method for preparing a semiconductor device is provided. The method includes forming a first dielectric layer over a semiconductor substrate, and forming a conductive contact penetrating through the first dielectric layer. The method also includes forming a lower landing pad over the conductive contact, and forming a second dielectric layer covering the lower landing pad. The method further includes etching the second dielectric layer to form a first opening exposing the lower landing pad, and forming an upper landing pad in the first opening.

Abstract: The present disclosure provides a semiconductor structure having a fin structure. The semiconductor includes a substrate defined with an active region. A first gate structure is disposed in the active region and includes a dielectric material. A second gate structure is disposed in the active region and includes the dielectric material. A fin structure having a first top surface is arranged to alternate with the first gate structure and the second gate structure. The first gate structure has a second top surface and the second gate structure has a third top surface. The second top surface and the third top surface are lower than the first top surface.

Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes: filling a trench of a stacking structure with a bottom anti-reflection coated material to form a dummy via in the trench, in which the stacking structure includes a low-k material layer and a cap layer, and the trench runs through the low-k material layer and the cap layer; and etching the dummy via by performing a first etching process and a second etching process.

Abstract: The present disclosure provides a semiconductor structure having a fin structure and a method of manufacturing the semiconductor structure. The semiconductor includes a substrate defined with an active region. A first gate structure is disposed in the active region and includes a dielectric material. A second gate structure is disposed in the active region and includes the dielectric material. A fin structure having a first top surface is arranged to alternate with the first gate structure and the second gate structure. The first gate structure has a second top surface and the second gate structure has a third top surface. The second top surface and the third top surface are lower than the first top surface.

Abstract: A semiconductor device includes a substrate, an oxide layer and a word line. The substrate has a plurality of protruding portions. Adjacent two of the protruding portions define a dense zone, and another adjacent two of the protruding portions define a loose zone. The oxide layer is disposed on the substrate. The word line is disposed on the substrate. A bottom surface of a portion of the word line in the dense zone and a bottom surface of a portion of the word line in the loose zone are substantially at the same height.

Abstract: The present disclosure provides a method of forming a semiconductor structure. The method comprises providing a substrate comprising an isolation region, an active region adjacent to the isolation region, and a first top surface, wherein the isolation region includes an isolation trench filled with a dielectric material, and the active region includes a gate trench filled with a gate electrode material; forming a hard mask on the substrate; and performing an etching process to partially remove portions of the dielectric material and gate electrode material exposed by the hard mask to form a second top surface of the dielectric material and a third top surface of the gate electrode material, wherein the second top surface and the third top surface are substantially at the same level and are substantially lower than the first top surface.