Patents by Inventor Min Fang

Min Fang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220181301
    Abstract: A die stack structure including a first semiconductor die, a second semiconductor die, an insulating encapsulation and a redistribution circuit structure is provided. The first semiconductor die includes a first semiconductor substrate including a first portion and a second portion, a first interconnect structure and a first bonding structure. The first interconnect structure is disposed on a top surface of the second portion, a lateral dimension of the first portion is greater than a lateral dimension of the top surface of the second portion. The second semiconductor die is disposed on the first semiconductor die and includes a second bonding structure, the second semiconductor die is electrically connected with the first semiconductor die through the first and second bonding structures. The insulating encapsulation is disposed on the first portion and laterally encapsulating the second portion and the second semiconductor die.
    Type: Application
    Filed: February 21, 2022
    Publication date: June 9, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Chao-Wen Shih, Min-Chien Hsiao, Nien-Fang Wu, Sung-Feng Yeh, Tzuan-Horng Liu
  • Patent number: 11349135
    Abstract: A method of preparation and application for a glass ceramic sealing thin strip with high sealing performance, differing from using conventional glass ceramic packaging paste applied to the junction of the cell stack assembly and connecting plates. The glass ceramic sealing thin strip of present invention utilizes tape casting to produce a single layer or multi-layer stacking in accordance with the required thickness of the glass-ceramic sealing thin strip, and cutting the glass ceramic sealing thin strips from molds in accordance with the geometry of cell stacks with equal thickness of the glass ceramic sealing thin strip for SOFC cell stack assembly, aiming to overcome the setbacks of the conventional dispensing method with glass ceramic packaging paste that makes the thickness difficult to control, and to effectively improve sealing performance of the cell stack assembly and the power generation efficiency, and achieve commercial application with mass production.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: May 31, 2022
    Assignee: INSTITUTE OF NUCLEAR ENERGY RESEARCH, ATOMIC ENERGY COUNCIL, EXECUTIVE YUAN
    Inventors: Tai-Nan Lin, Szu-Han Wu, Yi-Jing Wu, Min-Fang Han, Wei-Xin Kao, Hong-Yi Kuo, Chun-Yen Yeh, Yung-Neng Cheng, Ruey-Yi Lee
  • Patent number: 11335964
    Abstract: A cold plate for a battery module comprising a plurality of cells that produces heat as charging and discharging is disclosed. The cold plate includes a plurality of first fins distributed in a first subarea of the cold plate; and a plurality of second fins distributed in a second subarea of the cold plate; wherein a second fin coverage of the plurality of second fins distributed in the second subarea is smaller than a first fin coverage of the plurality of first fins distributed in the first subarea when an amount of heat absorption of the second subarea from the plurality of cells is greater than an amount of heat absorption of the first subarea from the plurality of cells.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: May 17, 2022
    Assignee: National Chung-Shan Institute of Science and Technology
    Inventors: Fu-Min Fang, Kuo-Kuang Jen, Gwo-Huei You, Kuo-An Liang
  • Patent number: 11317496
    Abstract: Provided is an LED lamp circuit, comprising an LED luminous component circuit, a rectifier circuit, and an output control circuit coupled between the LED luminous component circuit and the rectifier circuit. The LED luminous component circuit comprises at least one light-emitting diode. The rectifier circuit is configured to output a rectified voltage to the LED luminous component circuit. The output control circuit comprises a voltage regulator circuit and a control switch circuit. The voltage regulator circuit comprises a thermosensitive device and a voltage divider connected in series. The thermosensitive device can regulate the control voltage at both ends of the control switch circuit. To protect the LED lamp, the control switch circuit disconnects when the control voltage is less than the threshold voltage of the control switch circuit.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: April 26, 2022
    Assignee: CURRENT LIGHTING SOLUTIONS, LLC
    Inventors: Zhu Mao, Qi Long, Min Fang, Shuyi Qin, Bo Zhang, Fanbin Wang
  • Patent number: 11243915
    Abstract: A current file is obtained in the data. It is determined whether a similar historical file exists based on a sampled data block from at least one predetermined location in the current file. In response to non-existence of the similar historical file, the current file and corresponding metadata are stored on a file basis. In response to existence of the similar historical file, a deduplication operation is applied on the current file on a block basis.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: February 8, 2022
    Assignee: International Business Machines Corporation
    Inventors: Min Fang, JiaYang Zheng, GuoFeng Zhu
  • Publication number: 20220037682
    Abstract: A method of preparation and application for a glass ceramic sealing thin strip with high sealing performance, differing from using conventional glass ceramic packaging paste applied to the junction of the cell stack assembly and connecting plates. The glass ceramic sealing thin strip of present invention utilizes tape casting to produce a single layer or multi-layer stacking in accordance with the required thickness of the glass-ceramic sealing thin strip, and cutting the glass ceramic sealing thin strips from molds in accordance with the geometry of cell stacks with equal thickness of the glass ceramic sealing thin strip for SOFC cell stack assembly, aiming to overcome the setbacks of the conventional dispensing method with glass ceramic packaging paste that makes the thickness difficult to control, and to effectively improve sealing performance of the cell stack assembly and the power generation efficiency, and achieve commercial application with mass production.
    Type: Application
    Filed: August 3, 2020
    Publication date: February 3, 2022
    Inventors: TAI-NAN LIN, SZU-HAN WU, YI-JING WU, MIN-FANG HAN, WEI-XIN KAO, HONG-YI KUO, CHUN-YEN YEH, YUNG-NENG CHENG, RUEY-YI LEE
  • Publication number: 20210394157
    Abstract: Provided is a method of making colloidal selenium nanoparticles. The method includes the steps as follows: Step (A): providing a reducing agent and an aqueous solution containing a selenium precursor; Step (B): mixing the aqueous solution containing the selenium precursor and the reducing agent to form a mixture solution in a reaction vessel and heating the mixture solution to undergo a reduction reaction and produce a composition containing selenium nanoparticles, residues and a gas, and guiding the gas out of the reaction vessel, wherein an amount of the residues is less than 20% by volume of the mixture solution; and Step (C): dispersing the selenium nanoparticles with a medium to obtain the colloidal selenium nanoparticles. The method has advantages of simplicity, safety, time-effectiveness, cost-effectiveness, high yield and eco-friendliness.
    Type: Application
    Filed: July 23, 2020
    Publication date: December 23, 2021
    Inventors: Chung-Jung HUNG, Chun-Lun CHIU, Chia-Chi CHANG, Hsin-Chang HUANG, Teng-Chieh HSU, Meng-Hsiu CHIH, Jim-Min FANG
  • Publication number: 20210385923
    Abstract: A driving circuit is provided in this present disclosure, the driving circuit includes a voltage input module, a quick start module and a control module. The voltage input module includes a first input terminal and a second input terminal and is configured to receive an alternating current voltage and convert the alternating current voltage into a direct current voltage. The quick start module is coupled to the voltage input module and configured to receive the direct current voltage and convert the direct current voltage into a startup voltage. The control module is coupled to the quick start module and configured to receive the startup voltage and control a load, wherein the quick start module comprises a first resistor and a second resistor connected in series and is coupled between the first input terminal and the control module.
    Type: Application
    Filed: September 19, 2019
    Publication date: December 9, 2021
    Inventors: Zhu Mao, Min Fang, Zhangji Zhou, Shuyi Qin, Bo Zhang, Fanbin Wang
  • Patent number: 11179781
    Abstract: Provided is a method of making colloidal platinum nanoparticles. The method includes three consecutive steps: dissolving platinum powders by a halogen-containing oxidizing agent in HCl to obtain an inorganic platinum solution containing an inorganic platinum compound; adding a reducing agent into the same reaction vessel to form a mixture solution and heating the mixture solution to undergo a reduction reaction and produce a composition containing platinum nanoparticles, residues and a gas, and guiding the gas out of the reaction vessel, wherein the amount of the residues is less than 15% by volume of the mixture solution; and adding a medium into the same reaction vessel to disperse the platinum nanoparticles to obtain colloidal platinum nanoparticles. The method is simple, safe, time-effective, cost-effective, and has the advantage of high yield.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: November 23, 2021
    Assignee: TRIPOD NANO TECHNOLOGY CORPORATION
    Inventors: Lin Lu, Kuei-Sheng Fan, Chun-Lun Chiu Chiu, Han-Wu Yen, Hao-Chan Hsu, Chia-Yi Lin, Chi-Jiun Peng, Cheng-Ding Wang, Jim-Min Fang
  • Patent number: 11152462
    Abstract: A semiconductor device includes a semiconductive substrate, a first semiconductive fin and a second semiconductive fin extending upwards from the semiconductive substrate, an isolation structure at least partially between the first semiconductive fin and the second semiconductive fin, a first semiconductive raised portion and a second semiconductive raised portion. The first semiconductive raised portion extends upwards from the semiconductive substrate, is buried under the isolation structure, and is between the first semiconductive fin and the second semiconductive fin. A top surface of the first semiconductive fin is higher than a top surface of the first semiconductive raised portion. The second semiconductive raised portion extends upwards from the semiconductive substrate, is buried under the isolation structure, and is between the first semiconductive raised portion and the second semiconductive fin.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: October 19, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cong-Min Fang, Kang-Min Kuo, Shi-Min Wu
  • Patent number: 11074018
    Abstract: Embodiments include a load calculator, a workload analyzer, and a decision module. The load calculator generates an input/output (IO) record for an asset. The IO record includes a count of read operations and write operations corresponding to the asset from each of a plurality of sites. The workload analyzer collects the IO record and generates at least one of a write threshold and a read threshold. The decision module generates a request for at least one of a promotion and a copy of the asset in response to a determination that an operation has reached at least one of the write threshold and the read threshold for the asset.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: July 27, 2021
    Assignee: International Business Machines Corporation
    Inventors: Duo Chen, Min Fang, Da Liu, Jinyi Pu, Jiang Yu
  • Patent number: 11070512
    Abstract: Embodiments for server port virtualization for guest logical unit number (LUN) masking in a host direct attach configuration using a storage adapter in a computing environment by a processor. An F switch port is simulated by an N storage port to enable either N-port virtualization (NPV) or N-port identification (ID) virtualization (NPIV) in the host direct attach configuration by directly attaching the N server port to the N storage port. A domain name system (DNS) operation is performed to cause each virtualized N-port ID to be mapped to fiber channel (FC) IDs in domain format of domain, area, port.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: July 20, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Min Fang, Qing Wang, Wei Yin, Jiang Yu
  • Patent number: 11063039
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a first source region, a second source region, a first drain region, and a second drain region. The semiconductor device structure includes a first gate structure over the substrate and between the first source region and the first drain region. The semiconductor device structure includes a second gate structure over the substrate and between the second source region and the second drain region. A first thickness of the first gate structure is greater than a second thickness of the second gate structure. A first gate width of the first gate structure is less than a second gate width of the second gate structure.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: July 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cong-Min Fang, Chih-Lin Wang, Kang-Min Kuo
  • Publication number: 20210175561
    Abstract: A cold plate for a battery module comprising a plurality of cells that produces heat as charging and discharging is disclosed. The cold plate includes a plurality of first fins distributed in a first subarea of the cold plate; and a plurality of second fins distributed in a second subarea of the cold plate; wherein a second fin coverage of the plurality of second fins distributed in the second subarea is smaller than a first fin coverage of the plurality of first fins distributed in the first subarea when an amount of heat absorption of the second subarea from the plurality of cells is greater than an amount of heat absorption of the first subarea from the plurality of cells.
    Type: Application
    Filed: December 4, 2019
    Publication date: June 10, 2021
    Inventors: Fu-Min Fang, Kuo-Kuang Jen, Gwo-Huei You, Kuo-An Liang
  • Patent number: 10973101
    Abstract: A single-stage driver for an LED device, configured to be coupled between a power supply and the LED device, comprises: a rectifier, a DC-to-DC converter, a resistor and a controller. The rectifier is configured to be coupled to the power supply and convert an alternating voltage from the power supply into a first direct voltage. The DC-to-DC converter, which comprises at least two switches, is coupled between the rectifier and the LED device and configured to receive the first direct voltage and provide a constant current to the LED device. The resistor is configured to be coupled in series with the LED device. The controller is coupled between the resistor and the at least two switches, and configured to keep the current through the LED device stable around a predetermined current value by controlling the switches based on a voltage across the resistor, wherein all the at least two switches are turned on or off synchronously.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: April 6, 2021
    Assignee: CURRENT LIGHTING SOLUTIONS, LLC
    Inventors: Zhu Mao, Min Fang, Zhangji Zhou, Shuyi Qin, Fanbin Wang
  • Patent number: D918205
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: May 4, 2021
    Assignee: Microsoft Corporation
    Inventors: Simon Cameron Dearsley, Patrick T. Gaule, Min Fang
  • Patent number: D940713
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: January 11, 2022
    Assignee: Microsoft Corporation
    Inventors: Go Osaki, Min Fang, Simon Cameron Dearsley
  • Patent number: D944251
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: February 22, 2022
    Assignee: Microsoft Corporation
    Inventors: Benjamin S. Peterson, Patrick T. Gaule, Min Fang, Aditha May Adams, Simon Cameron Dearsley
  • Patent number: D944252
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: February 22, 2022
    Assignee: Microsoft Corporation
    Inventors: Benjamin S. Peterson, Patrick T. Gaule, Min Fang, Aditha May Adams, Simon Cameron Dearsley
  • Patent number: D949860
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: April 26, 2022
    Assignee: Microsoft Corporation
    Inventors: Jinwon Yook, Min Fang, Simon Cameron Dearsley