Abstract: Embodiments of the invention include a semiconductor structure having nanosheets separated by inner spacers, the inner spacers having a curved portion in a dimension. The semiconductor structure includes source/drain regions formed adjacent to the nanosheets and gate material formed on the nanosheets.

Abstract: A semiconductor integrated circuit (IC) device that includes an angled gate cut region, a first transistor associated with a first gate, and a second transistor associated with a second gate. The angled gate cut region may be angled such that its top surface area is nearest a boundary of the first transistor and its bottom surface area is nearest a boundary of the second transistor. The angled gate cut region may separate the first gate from the second gate and may further separate the source/drain regions of the first transistor from the source/drain regions of the second transistor. The angled gate cut region may provide for adequate frontside surface area of the first gate to which a frontside gate contact may connect and may further provide for adequate backside surface area of the second gate to which a backside gate contact may connect.

Abstract: The present disclosure describes an illustrative semiconductor IC device that includes a integrated logic microdevice and a memory microdevice that share the same vertical channel. By utilizing the same vertical channel, the overall footprint area of the integrated logic microdevice and the memory microdevice is relatively reduced and allows for further scaling of the associated semiconductor IC device.

Abstract: A SRAM is provided that includes a first pull-up transistor having a first channel length, and a first pull-down transistor located adjacent to the first pull-up transistor and having a second channel length, wherein the second channel length is greater than the first channel length. The structure further includes a first backside contact structure contacting a first n-doped source/drain region of the first pull-down transistor, wherein the first backside contact structure has a first critical dimension that is constant throughout an entirety thereof, and a second backside contact structure having a vertical portion and a base portion. The vertical portion of the second backside contact structure directly contacts a first p-doped source/drain region of the first pull-up transistor and the base portion of the second backside contact structure has a second critical dimension that is greater than the first critical dimension.

Abstract: A method to co-integrate a metal trench cut for aggressively scaled contact tip-to-tip and wrap-around-contact formation is provided. A semiconductor device made from the method is also provided in which a metal trench cut region and wrap-around-contacts are present.

Abstract: A semiconductor device that includes a stack of nanostructure material layers overlying a substrate, wherein a gate all around structure is present on a channel region portion for the stack of nanostructure material layers. A bottom source and drain region is present on a first side of the channel region portion, wherein the bottoms source and drain region is composed by a first epitaxial semiconductor material that has a confinement sidewall spacer in direct contact with sidewalls of the first epitaxial semiconductor material defining a lateral dimension for the epitaxial semiconductor material. An upper source and drain region is present on a second side of the channel region portion for the stack of nanostructure material layers. The upper source and drain region is composed of a second epitaxial semiconductor material that partially extends over the confinement sidewall spacer.

Abstract: A semiconductor device that includes a stack of nanostructure material layers overlying a substrate, wherein a gate all around structure is present on a channel region portion for the stack of nanostructure material layers, and source and drain semiconductor contacts on each side of the gate all around structure. The source and drain semiconductor contacts are in direct contact with edges of the channel region portion for the stack of nanostructure material layers. A gate spacer between the source and drain semiconductor contacts and the gate all around structure. An electrically insulating substrate isolation layer aligned to be between the gate all around structure, the gate spacer and the substrate. A base portion of the gate spacer has an L-shaped geometry including a portion that warps over an upper surface of the electrically insulating substrate isolation layer.

Abstract: A semiconductor device comprises a first nanosheet transistor disposed on a semiconductor substrate, the first nanosheet transistor comprising a plurality of first gate structures, and a second nanosheet transistor disposed on the semiconductor substrate, the second nanosheet transistor comprising a plurality of second gate structures. Respective stacked spacer structures are disposed on respective sides of respective ones of the plurality of second gate structures, wherein each of the respective stacked spacer structures comprises a first spacer and a second spacer. Respective ones of the plurality of first gate structures comprise a first nanosheet gate portion and a gate dielectric layer around the first nanosheet gate portion. The respective ones of the plurality of second gate structures comprise a second nanosheet gate portion and at least two gate dielectric layers around the second nanosheet gate portion.

Abstract: Embodiments of the invention include a semiconductor structure having a first transistor having first nanosheets as first channel regions, a second transistor having second nanosheets as second channel regions, and a third transistor having third nanosheets as third channel regions. The first, second, and third nanosheets are formed of nanosheet material, where the first nanosheets are fewer in number than the second nanosheets. The semiconductor structure includes first end portions formed of the nanosheet material between first inner spacers in the first transistor. The first end portions are opposite one another and discontinuous in the first transistor.

Abstract: A semiconductor device fabrication method is provided and includes building first and second nanosheet devices, locating a dielectric bar between the first and second nanosheet devices, forming, in the first nanosheet device, a first work function metal (WFM) and forming in the second nanosheet device, a second WFM that extends across the dielectric bar and the first WFM.

Abstract: Embodiments of present invention provide a static random-access-memory (SRAM). The SRAM includes a first and a second pull-down (PD) transistor having respectively a first and a fourth set of nanosheets of a first width; a first and a second pass-gate (PG) transistor having respectively a second and a fifth set of nanosheets of a second width; and a first and a second pull-up (PU) transistor having respectively a third and a sixth set of nanosheets of a third width, wherein the first width is wider than the second width, the second width is wider than the third width, the first set of nanosheets is substantially aligned with the second set of nanosheets at one side of the first and second sets of nanosheets, and the fourth set of nanosheets is substantially aligned with the fifth set of nanosheets at one side of the fourth and fifth sets of nanosheets.

Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a gate structure with a first portion having a first top surface and a second portion having a second top surface, the first top surface being above the second top surface; a dielectric cap layer on top of the second portion of the gate structure, the first portion of the gate structure being embedded in the dielectric cap layer; and a gate contact being above and substantially aligned with the first portion of the gate structure. A method of forming the same is also provided.

Abstract: A semiconductor device fabrication method is provided and includes forming first and second stacks each including a dual layer top dielectric cap (TDC), sequentially surrounding each layer and a portion of the dual layer TDC of the first stack with high-k dielectric, a first work function metal (WFM) and a second WFM, sequentially surrounding each layer and a portion of the dual layer TDC of the second stack with the high-k dielectric and the second WFM, forming gate metal around the first and second stacks and recessing the gate metal and the second WFM to a depth defined above a height of an uppermost first WFM horizontal portion.

Abstract: A semiconductor device includes a plurality of first nanosheet fin structures located in a dense array region of a substrate. The semiconductor device further includes a plurality of first isolation trenches between adjacent first nanosheet fin structures of the plurality of first nanosheet fin structures. The plurality of first isolation trenches include: a first trench isolation layer, a protective liner formed on top of the first trench isolation layer, and a second trench isolation layer located above the protective liner. The protective liner separates the first trench isolation layer from the second trench isolation layer and the first trench isolation layer is more dense than the second trench isolation layer.

Abstract: A semiconductor device, includes a source and drain bottom epitaxial layer positioned on top of a dielectric substrate. A metal gate is positioned on top of the bottom epitaxial layer. A source and drain top epitaxial layer is positioned on top of the metal gate. A first and second semiconductor channel pass vertically from the source and drain top epitaxial layer through the metal gate to the source and drain bottom epitaxial layer. First and second metal contacts are conductively coupled to the first and second semiconductor channels. First and second metal vias are formed on a backside of the source and drain bottom epitaxial layer and arranged in conductive contact with the first and second semiconductor channels. A metal layer is formed on a backside of the first and second metal vias.

Abstract: A Tunnel Field-Effect Transistor (TFET) device, an isolating layer over a substrate layer, a gate stack above the isolating layer, a source and a drain region over the isolating layer, a channel region underneath the gate stack, and a plurality of nanosheets in the channel region protruding from the source region. Each nanosheet of the plurality of nanosheets includes source region material encapsulated by a narrow band gap material.

Abstract: Provided is a stacked field-effect transistor (FET). The stacked FET comprises a top device, a bottom device, and a transition region between the top device and the bottom device. The transition region includes a plurality of inner spacers and a first inter-layer dielectric (ILD). The ILD is formed between each of the plurality of inner spacers. The top and bottom devices have a first channel sheet thickness in a gate region and a second channel sheet thickness between inner spacers. The second channel sheet thickness is larger than both the first channel sheet thickness and the first distance.

Abstract: Embodiments of the invention are directed to an integrated circuit (IC) that includes a channel that includes a nanosheet stack; an etch-stop isolation (ESI) region over the nanosheet stack; and a portion of a first type of gate element between the ESI region and the nanosheet stack. The ESI region is operable to prevent etching the portion of the first type of gate element that is between the ESI region and the nanosheet stack.

Abstract: A semiconductor device is provided and includes gate regions interleaved between interlayer dielectric (ILD) regions, field effect transistor (FET) structures extending across the gate regions and the ILD regions, source and drain (S/D) regions, shared between the gate regions, at exterior ones of the ILD regions, dielectric material between the FET structures and bisecting the gate regions and the ILD regions, liner material and contacts. The liner material is disposed on opposite sides of the dielectric material in the gate regions and not in the ILD regions. The contacts are formed about the FET structures in the exterior ones of the ILD regions and across the dielectric material at an interior one of the ILD regions.

Abstract: A semiconductor structure includes a nanosheet field-effect transistor having a nanosheet stack structure, and a fin field-effect transistor having a set of vertical fins. Each of the vertical fins includes an oxide semiconductor material. The nanosheet field-effect transistor and the fin field-effect transistor are in a stacked configuration.