Patents by Inventor Min-Hsiu Tsai

Min-Hsiu Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11222818
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a fin structure over a semiconductor substrate and forming a gate stack over the fin structure. The method also includes forming an epitaxial structure over the fin structure, and the epitaxial structure is adjacent to the gate stack. The method further includes forming a dielectric layer over the epitaxial structure and forming an opening in the dielectric layer to expose the epitaxial structure. In addition, the method includes applying a metal-containing material on the epitaxial structure while the epitaxial structure is heated so that a portion of the epitaxial structure is transformed to form a metal-semiconductor compound region.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: January 11, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Hsiang Chao, Min-Hsiu Hung, Chun-Wen Nieh, Ya-Huei Li, Yu-Hsiang Liao, Li-Wei Chu, Kan-Ju Lin, Kuan-Yu Yeh, Chi-Hung Chuang, Chih-Wei Chang, Ching-Hwanq Su, Hung-Yi Huang, Ming-Hsing Tsai
  • Patent number: 11182524
    Abstract: A fixing device and a fixing method for a clock tree are provided. The fixing method for the clock tree includes: performing a clock signal path tracking operation on a netlist of a circuit according to timing constraint information to obtain a clock tree circuitry structure; identifying a convergency status of the clock tree circuitry structure to find out at least one clock convergence point, and setting one of a plurality of clock signals on the clock convergence point as a selected clock signal; performing a fix point identification operation on the clock tree circuitry structure based on the selected clock signal to obtain a plurality of candidate fix points; and calculating a plurality weighting values of the candidate fix points, obtaining a plurality of selected fixed points according to the weighting values.
    Type: Grant
    Filed: January 8, 2021
    Date of Patent: November 23, 2021
    Assignees: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Yuan Kao, Hsin-Lung Li, Min-Hsiu Tsai
  • Publication number: 20210341962
    Abstract: An apparatus for adjusting skew of circuit signal and an adjusting method thereof are provided. The adjusting method includes: providing a controller for executing: based on each of a plurality of clock signals, dividing a circuit to generate a plurality of circuit partitions according to a netlist of the circuit; grouping the circuit partitions to respectively generate a plurality of circuit groups; identifying adjacent states of layout areas of the circuit groups; and, adjusting a skew value of each of the circuit groups according to the adjacent states.
    Type: Application
    Filed: July 7, 2020
    Publication date: November 4, 2021
    Applicants: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tse-Wei Wu, Chen-Yuan Kao, Min-Hsiu Tsai
  • Publication number: 20210303767
    Abstract: An establishing method for the timing model includes: identifying at least one first victim path which is a boundary path in a circuit block; determining whether to remove a first aggressor path corresponding to the first victim path according to a transmission delay on the first victim path; finding a plurality of high-fanout circuit devices with a fanout number greater than a preset value in the circuit block; determining whether to remove each of the high-fanout circuit devices according to a connection position of each of the high-fanout circuit devices; identifying a plurality of second victim paths corresponding to each of the high-fanout circuit devices, and determining whether to keep or remove a second aggressor path corresponding to each of the second victim paths according to a transmission delay of each of the second victim paths.
    Type: Application
    Filed: May 3, 2020
    Publication date: September 30, 2021
    Applicants: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsin-Hsiung Liao, Min-Hsiu Tsai
  • Publication number: 20210173171
    Abstract: An optical element driving mechanism has an optical axis and includes a fixed portion, a movable portion, and a driving assembly. The movable portion is movable relative to the fixed portion. The driving assembly drives the movable portion to move relative to the fixed portion. The driving assembly moves in a first direction to move the movable portion in a second direction, wherein the first direction is different from the second direction.
    Type: Application
    Filed: December 4, 2020
    Publication date: June 10, 2021
    Inventors: Jungsuck RYOO, Chieh-An CHANG, Min-Hsiu TSAI, Chao-Chang HU, Shu-Shan CHEN, Pai-Jui CHENG, Chao-Hsi WANG
  • Publication number: 20210149143
    Abstract: The present disclosure provides an optical element driving mechanism, which includes a movable assembly, a fixed assembly, and a driving assembly. The movable assembly is configured to be connected to an optical element. The movable assembly is movable relative to the fixed assembly. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly in a range of motion. The optical element driving mechanism further includes a positioning assembly configured to position the movable assembly at a predetermined position relative to the fixed assembly when the driving assembly is not operating.
    Type: Application
    Filed: November 13, 2020
    Publication date: May 20, 2021
    Inventors: Chao-Chang HU, Kuen-Wang TSAI, Liang-Ting HO, Chao-Hsi WANG, Chih-Wei WENG, He-Ling CHANG, Che-Wei CHANG, Sheng-Zong CHEN, Ko-Lun CHAO, Min-Hsiu TSAI, Shu-Shan CHEN, Jungsuck RYOO, Mao-Kuo HSU, Guan-Yu SU
  • Publication number: 20210132360
    Abstract: An optical system is provided. The optical system includes a first optical module and a second optical module. The first optical module is used for connected to a first optical element. The second optical module is used for connected to a second optical element. A light enters the first optical module along an incident direction, and the light is adjusted by the first optical module to enter the second optical module along a first direction. The incident direction is not parallel with the first direction.
    Type: Application
    Filed: October 30, 2020
    Publication date: May 6, 2021
    Inventors: Jungsuck RYOO, Chao-Chang HU, Shu-Shan CHEN, Min-Hsiu TSAI, Chieh-An CHANG
  • Publication number: 20210132319
    Abstract: An optical element driving mechanism has an optical axis and includes a fixed portion, a movable portion, and a driving assembly. The movable portion is movable relative to the fixed portion. The driving assembly drives the movable portion to move relative to the fixed portion, wherein the driving assembly moves along a first direction to move the movable portion along a second direction, the first direction is different from the second direction.
    Type: Application
    Filed: June 12, 2020
    Publication date: May 6, 2021
    Inventors: Chao-Chang HU, Shu-Shan CHEN, Jungsuck RYOO, Min-Hsiu TSAI, Chieh-An CHANG, Pai-Jui CHENG
  • Publication number: 20210080681
    Abstract: An optical system is provided. The optical system includes a first optical module. The first optical module includes a first fixed portion, a first movable portion, a first driving assembly, and a circuit assembly. The first movable portion is used for connecting to a first optical element, and the first movable portion is movably connected to the fixed portion. The first driving assembly is used for driving the first movable portion to move relative to the first fixed portion. The circuit assembly is electrically connected to the first driving assembly.
    Type: Application
    Filed: June 12, 2020
    Publication date: March 18, 2021
    Inventors: Jungsuck RYOO, Pai-Jui CHENG, Chao-Chang HU, Min-Hsiu TSAI, Shu-Shan CHEN, Chieh-An CHANG
  • Patent number: 10909291
    Abstract: A method for increasing coverage of a scan test, executed by at least one processor, includes following operations: analyzing a first netlist file and a second netlist file to acquire a change of a circuit structure, in which the first netlist file corresponds to a first scan chain circuitry, and the second netlist file corresponds to a second scan circuitry wherein the second netlist file is generated by processing the first netlist file with executing an engineering change order (ECO); repairing the second scan chain circuitry according to at least one predetermined criterion; evaluating a candidate node of the repaired second scan chain circuitry, to connect a new flip flop circuit generated after executing the ECO to the candidate node; and storing the second netlist file being processed as a third netlist file, to fabricate an integrated circuit.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: February 2, 2021
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Tse-Wei Wu, Yu-Hsun Su, Chen-Yuan Kao, Min-Hsiu Tsai
  • Publication number: 20200393637
    Abstract: An optical system is provided. The optical system includes a first optical module. The first optical module includes a fixed portion, a movable portion, a driving assembly, and a circuit assembly. The movable portion is movably connected to the fixed portion, and the movable portion is used to connect to an optical element. The driving assembly is used to drive the movable portion to move relative to the fixed portion. The circuit assembly is electrically connected to the driving assembly.
    Type: Application
    Filed: June 12, 2020
    Publication date: December 17, 2020
    Inventors: Jungsuck RYOO, Pai-Jui CHENG, Chao-Chang HU, Min-Hsiu TSAI, Shu-Shan CHEN, Chieh-An CHANG
  • Publication number: 20200380189
    Abstract: A method for increasing coverage of a scan test, executed by at least one processor, includes following operations: analyzing a first netlist file and a second netlist file to acquire a change of a circuit structure, in which the first netlist file corresponds to a first scan chain circuitry, and the second netlist file corresponds to a second scan circuitry wherein the second netlist file is generated by processing the first netlist file with executing an engineering change order (ECO); repairing the second scan chain circuitry according to at least one predetermined criterion; evaluating a candidate node of the repaired second scan chain circuitry, to connect a new flip flop circuit generated after executing the ECO to the candidate node; and storing the second netlist file being processed as a third netlist file, to fabricate an integrated circuit.
    Type: Application
    Filed: December 4, 2019
    Publication date: December 3, 2020
    Inventors: Tse-Wei WU, Yu-Hsun SU, Chen-Yuan KAO, Min-Hsiu TSAI
  • Patent number: 10817633
    Abstract: A timing model building method, for building a timing model corresponding to a gate-level netlist of a block, includes the following operations: utilizing a processor to generate an interface net of the gate-level netlist, where if the gate-level netlist comprises an unconstrained clock tree and boundary timing constraint information of the gate-level netlist does not comprise a timing constraint of the unconstrained clock tree, the interface net comprises none of cells of the gate-level netlist driven by the unconstrained clock tree; utilizing the processor to generate an identified internal net of the gate-level netlist, where the identified internal net is cross-coupled to the interface net; and utilizing the processor to generate the timing model according to the interface net and the identified internal net.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: October 27, 2020
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Hsiu Tsai, Hsin-Hsiung Liao, Min-Hsiu Tsai
  • Publication number: 20200311218
    Abstract: A timing model building method, for building a timing model corresponding to a gate-level netlist of a block, includes the following operations: utilizing a processor to generate an interface net of the gate-level netlist, where if the gate-level netlist comprises an unconstrained clock tree and boundary timing constraint information of the gate-level netlist does not comprise a timing constraint of the unconstrained clock tree, the interface net comprises none of cells of the gate-level netlist driven by the unconstrained clock tree; utilizing the processor to generate an identified internal net of the gate-level netlist, where the identified internal net is cross-coupled to the interface net; and utilizing the processor to generate the timing model according to the interface net and the identified internal net.
    Type: Application
    Filed: May 30, 2019
    Publication date: October 1, 2020
    Inventors: Meng-Hsiu TSAI, Hsin-Hsiung LIAO, Min-Hsiu TSAI
  • Publication number: 20200271895
    Abstract: A driving mechanism is provided, including a fixed part, a movable part for holding an optical element, and a driving assembly. The movable part is movable relative to the fixed part and has a first resonance frequency with respect to the fixed part. The driving assembly is configured to drive the movable part to rotate back and forth within a range relative to the fixed part.
    Type: Application
    Filed: January 9, 2020
    Publication date: August 27, 2020
    Inventors: Kai-Jing FU, Chao-Chang HU, Min-Hsiu TSAI, Mao-Kuo HSU, Juei-Hung TSAI
  • Publication number: 20200209520
    Abstract: A driving mechanism is provided, including a fixed part, a movable part for holding an optical element, a driving assembly, and a positioning structure. The movable part is connected to the fixed part. The driving assembly is configured to drive the movable part to move relative to the fixed part. The positioning structure is formed on the movable part or the fixed part for positioning the optical element or at least one part of the driving assembly.
    Type: Application
    Filed: December 27, 2019
    Publication date: July 2, 2020
    Inventors: Kai-Jing FU, Chao-Chang HU, Min-Hsiu TSAI, Mao-Kuo HSU, Juei-Hung TSAI
  • Patent number: 10614260
    Abstract: A model-building method comprises following operations: reading a top netlist and a block model, wherein the top netlist comprises a first input node, a first output node and a multivibrator, the block model comprises a input node and a output node; obtaining a first subnetlist from the top netlist, wherein the first subnetlist comprises a component coupled between the input node and the first input node or the multivibrator; obtaining a second subnetlist from the top netlist, wherein the second subnetlist comprises a component coupled between the output node and the first output node or the multivibrator; obtaining a third subnetlist from the top netlist, wherein the third subnetlist comprises a component coupled between a clock input node of the multivibrator and a top clock input node of the top netlist; generating a top ILM according to the first to the third subnetlist.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: April 7, 2020
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Hsiu Tsai, Hsin-Hsiung Liao, Min-Hsiu Tsai
  • Publication number: 20190294746
    Abstract: A model-building method comprises following operations: reading a top netlist and a block model, wherein the top netlist comprises a first input node, a first output node and a multivibrator, the block model comprises a input node and a output node; obtaining a first subnetlist from the top netlist, wherein the first subnetlist comprises a component coupled between the input node and the first input node or the multivibrator; obtaining a second subnetlist from the top netlist, wherein the second subnetlist comprises a component coupled between the output node and the first output node or the multivibrator; obtaining a third subnetlist from the top netlist, wherein the third subnetlist comprises a component coupled between a clock input node of the multivibrator and a top clock input node of the top netlist; generating a top ILM according to the first to the third subnetlist.
    Type: Application
    Filed: May 30, 2018
    Publication date: September 26, 2019
    Inventors: Meng-Hsiu TSAI, Hsin-Hsiung LIAO, Min-Hsiu TSAI
  • Patent number: 10311185
    Abstract: A model-building method and a model-building system for executing the method are disclosed. The method includes the following steps: reading a first netlist; extracting a netlist between an input and an initial-stage clock multi-vibrator and extracting a netlist between a final-stage clock multi-vibrator and an output from the first netlist; extracting a netlist between the input and the output from the first netlist; extracting a netlist between a first clock multi-vibrator and a second clock multi-vibrator from the first netlist; extracting netlists between the first clock input and the initial-stage clock multi-vibrator and the first clock multi-vibrator from the first netlist; extracting netlists between the second clock input and the final-stage clock multi-vibrator and the second clock multi-vibrator from the first netlist; and generating a second netlist based on extracted netlists.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: June 4, 2019
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Hsiung Liao, Min-Hsiu Tsai
  • Publication number: 20180330033
    Abstract: A model-building method and a model-building system for executing the method are disclosed. The method includes the following steps: reading a first netlist; extracting a netlist between an input and an initial-stage clock multi-vibrator and extracting a netlist between a final-stage clock multi-vibrator and an output from the first netlist; extracting a netlist between the input and the output from the first netlist; extracting a netlist between a first clock multi-vibrator and a second clock multi-vibrator from the first netlist; extracting netlists between the first clock input and the initial-stage clock multi-vibrator and the first clock multi-vibrator from the first netlist; extracting netlists between the second clock input and the final-stage clock multi-vibrator and the second clock multi-vibrator from the first netlist; and generating a second netlist based on extracted netlists.
    Type: Application
    Filed: September 19, 2017
    Publication date: November 15, 2018
    Inventors: Hsin-Hsiung LIAO, Min-Hsiu TSAI