Abstract: A semiconductor device assembly includes a substrate and a first semiconductor device mounted to the substrate. An epoxy-based spacer is mounted to the substrate proximate to the first semiconductor device by an adhesive attached to a bottom surface of the epoxy-based spacer and to the substrate. A second semiconductor device is mounted directly to top surfaces of both the first semiconductor device and the epoxy-based spacer.

Abstract: An MRAM structure includes a dielectric layer. A first MRAM, a second MRAM and a third MRAM are disposed on the dielectric layer, wherein the second MRAM is disposed between the first MRAM and the third MRAM, and the second MRAM includes an MTJ. Two gaps are respectively disposed between the first MRAM and the second MRAM and between the second MRAM and the third MRAM. Two tensile stress pieces are respectively disposed in each of the two gaps. A first compressive stress layer surrounds and contacts the sidewall of the MTJ entirely. A second compressive stress layer covers the openings of each of the gaps and contacts the two tensile stress pieces.

Abstract: Semiconductor devices and associated systems and methods are disclosed herein. In some embodiments, the semiconductor devices include a package substrate, a stack of dies carried by the package substrate, and one or more radiation shields configured to absorb neutrons from neutron radiation incident on the semiconductor device. The radiation shields can include one or more walls attached to a perimeter portion of the package substrate at least partially surrounding the stack of dies and/or a lid carried over the stack of dies. Each of the radiation shields can include hydrocarbon materials, boron, lithium, gadolinium, cadmium, and like materials that effectively absorb neutrons from neutron radiation. In some embodiments, the semiconductor devices also include a molding material over the stack of dies and the radiation shields, and a hydrocarbon coating over an external surface of the mold material.

Abstract: An industrial work order analysis system applies statistical and machine learning analytics to both open and closed work orders to identify problems and abnormalities that could impact manufacturing and maintenance operations. The analysis system applies algorithms to learn normal maintenance behaviors or characteristics for different types of maintenance tasks and to flag abnormal maintenance behaviors that deviate significantly from normal maintenance procedures. Based on this analysis, embodiments of the work order analysis system can identify unnecessarily costly maintenance procedures or practices, as well as predict asset failures and offer enterprise-specific recommendations intended to reduce machine downtime and optimize the maintenance process.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a metal gate on a substrate, a spacer around the metal gate, and a first interlayer dielectric (ILD) layer around the spacer, performing a plasma treatment process to transform the spacer into a first bottom portion and a first top portion, performing a cleaning process to remove the first top portion, and forming a second ILD layer on the metal gate and the first ILD layer.

Abstract: Semiconductor devices having flow controllers configured to reduce mitigation of mold material between stacked layers, and associated systems and methods, are disclosed herein. In some embodiments, the semiconductor device includes a package substrate that has first and second surfaces. First and second die stacks are formed on the first surface and are adjacent to each other. A portion of the first surface extends between the first and second die stacks. A layer of material is adhered to top surfaces of the first and second die stacks and extends at a distance above the package substrate to form a tunnel between the layer of material, opposing sidewalls of the die stacks, and the package substrate. The semiconductor device further includes a flow controller that is adhered to at least a portion of the first surface inside the tunnel that reduces a cross-sectional surface area of at least a portion of the tunnel.

Abstract: An MRAM structure includes a dielectric layer. A first MRAM, a second MRAM and a third MRAM are disposed on the dielectric layer, wherein the second MRAM is disposed between the first MRAM and the third MRAM, and the second MRAM includes an MTJ. Two gaps are respectively disposed between the first MRAM and the second MRAM and between the second MRAM and the third MRAM. Two tensile stress pieces are respectively disposed in each of the two gaps. A first compressive stress layer surrounds and contacts the sidewall of the MTJ entirely. A second compressive stress layer covers the openings of each of the gaps and contacts the two tensile material pieces.

Abstract: The application discloses a cabinet lighting power-taking system including a cabinet, a power-taking assembly and lamps. The power-taking assembly includes at least one wire-distribution box, which is attached to and installed on a surface of the cabinet and is provided with a power-input interface and a plurality of power-output interfaces, so as to separate a single power-output interface into the plurality of power-output interfaces in parallel through shunt conversion. The power-input interface is configured for connecting a commercial power. The lamps are installed in the cabinet and plugged into the plurality of power-output interfaces one by one. This application improves an installation structure of the cabinet lighting power-taking system, and provides a structure that does not require slotting and wiring, which facilitates a process of installation, improves the efficiency of installation and optimizes the safety of using the lamps.

Abstract: Semiconductor devices having flow controllers configured to reduce mitigation of mold material between stacked layers, and associated systems and methods, are disclosed herein. In some embodiments, the semiconductor device includes a package substrate that has first and second surfaces. First and second die stacks are formed on the first surface and are adjacent to each other. A portion of the first surface extends between the first and second die stacks. A layer of material is adhered to top surfaces of the first and second die stacks and extends at a distance above the package substrate to form a tunnel between the layer of material, opposing sidewalls of the die stacks, and the package substrate. The semiconductor device further includes a flow controller that is adhered to at least a portion of the first surface inside the tunnel that reduces a cross-sectional surface area of at least a portion of the tunnel.

Abstract: The application discloses a cabinet lighting power-taking system including a cabinet, a power-taking assembly and lamps. The power-taking assembly includes at least one wire-distribution box, which is attached to and installed on a surface of the cabinet and is provided with a power-input interface and a plurality of power-output interfaces, so as to separate a single power-output interface into the plurality of power-output interfaces in parallel through shunt conversion. The power-input interface is configured for connecting a commercial power. The lamps are installed in the cabinet and plugged into the plurality of power-output interfaces one by one. This application improves an installation structure of the cabinet lighting power-taking system, and provides a structure that does not require slotting and wiring, which facilitates a process of installation, improves the efficiency of installation and optimizes the safety of using the lamps.

Abstract: An MRAM structure includes a dielectric layer. A first MRAM, a second MRAM and a third MRAM are disposed on the dielectric layer, wherein the second MRAM is disposed between the first MRAM and the third MRAM, and the second MRAM includes an MTJ. Two gaps are respectively disposed between the first MRAM and the second MRAM and between the second MRAM and the third MRAM. Two tensile stress pieces are respectively disposed in each of the two gaps. A first compressive stress layer surrounds and contacts the sidewall of the MTJ entirely. A second compressive stress layer covers the openings of each of the gaps and contacts the two tensile material pieces.

Abstract: A random access method and a device are provided, to enable a device in the Internet of Things to implement random access. The method includes: selecting, by a terminal from at least two frequencies, frequencies used to send a physical random access channel PRACH signal, as frequencies occupied by target PRACH resources, where the at least two frequencies each have a preset bandwidth, and there is no intersection between frequency bands of the at least two frequencies; generating, by the terminal, a target PRACH signal based on the frequencies occupied by the target PRACH resources, a root allocated by a base station, and a cyclic shift corresponding to the root allocated by the base station; and sending, by the terminal, the target PRACH signal to the base station on the target PRACH resources.

Abstract: A random access method and a device are provided, to enable a device in the Internet of Things to implement random access. The method includes: selecting, by a terminal from at least two frequencies, frequencies used to send a physical random access channel PRACH signal, as frequencies occupied by target PRACH resources, where the at least two frequencies each have a preset bandwidth, and there is no intersection between frequency bands of the at least two frequencies; generating, by the terminal, a target PRACH signal based on the frequencies occupied by the target PRACH resources, a root allocated by a base station, and a cyclic shift corresponding to the root allocated by the base station; and sending, by the terminal, the target PRACH signal to the base station on the target PRACH resources.

Abstract: A memory interface includes a buffer for storing requests for accessing a volatile memory, which includes at least two ranks of memory cell of a memory channel The memory interface monitors the requests to access each rank in the buffer. Upon detecting from the requests that a given rank of the at least two ranks is to be idle for a time period exceeding a time threshold, the circuitry signals a controller to command the given rank to enter a self-refresh mode independent of a refresh mode of other ranks. The memory interface is coupled to a processor, which executes an operating system (OS) kernel to prioritize memory allocation from a prioritized rank of the at least two ranks over the given rank, and migrates allocated memory blocks from the given rank to the prioritized rank to increase a probability of idleness of the given rank.

Abstract: Embodiments of the present disclosure provide an information processing method, apparatus and system. The method includes: one or more interface adapters, each interface adapter being connected to an outer application system, configured to achieve data interaction and function call between the multiple outer application systems; and a centralized rules engine connected to the one or more interface adapters and configured to use a preset rule to control the data interaction and function call between the multiple outer application systems connected to the interface adapters. Hence, a general interface and control rule is redesigned, application integration can be achieved more easily, extensibility is good, and independence of individual integrated applications is not affected.

Abstract: The present invention provides a method for managing memory space in an electronic device including: selecting a candidate page from a first memory space for swapping the candidate page out of the first memory space into the second memory space; compressing the candidate page to obtain a first compressed page and a first hash value of the first compressed page; performing a comparison using the first hash value of the first compressed page and the hash values of the pages stored in a second memory space to find whether the pages have the same content as the first compressed page or the candidate page; and if a page is found to have the same content as the first compressed page or the candidate page, mapping a virtual address of the first compressed page or the candidate page to the found page.

Abstract: A memory interface includes a buffer for storing requests for accessing a volatile memory, which includes at least two ranks of memory cell of a memory channel The memory interface monitors the requests to access each rank in the buffer. Upon detecting from the requests that a given rank of the at least two ranks is to be idle for a time period exceeding a time threshold, the circuitry signals a controller to command the given rank to enter a self-refresh mode independent of a refresh mode of other ranks. The memory interface is coupled to a processor, which executes an operating system (OS) kernel to prioritize memory allocation from a prioritized rank of the at least two ranks over the given rank, and migrates allocated memory blocks from the given rank to the prioritized rank to increase a probability of idleness of the given rank.

Abstract: A palm wrench includes a C-shaped body and a driving head. The driving head is pivotably and rotatably located within the body. The body has an opening, and the driving head has two function ends on two sides thereof. The driving head is pivotably connected to the body by two pivots which extend through the body and are connected to the driving head. The driving head can be rotated with respect to the body, and the user can grapes the body to rotate the driving head to output torque.

Abstract: Embodiments of the present disclosure provide an information processing method, apparatus and system. The method includes: one or more interface adapters, each interface adapter being connected to an outer application system, configured to achieve data interaction and function call between the multiple outer application systems; and a centralized rules engine connected to the one or more interface adapters and configured to use a preset rule to control the data interaction and function call between the multiple outer application systems connected to the interface adapters. Hence, a general interface and control rule is redesigned, application integration can be achieved more easily, extensibility is good, and independence of individual integrated applications is not affected.