Patents by Inventor Min-hwan Kim

Min-hwan Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150125357
    Abstract: A gas reactor device includes a plurality of microcavities or microchannels defined at least partially within a thick metal oxide layer consisting essentially of defect free oxide. Electrodes are arranged with respect to the microcavities or microchannels to stimulate plasma generation therein upon application of suitable voltage. One or more or all of the electrodes are encapsulated within the thick metal oxide layer. A gas inlet is configured to receive feedstock gas into the plurality of microcavities or microchannels. An outlet is configured to outlet reactor product from the plurality of microcavities or microchannels. In an example preferred device, the feedstock gas is air or O2 and is converted by the plasma into ozone (O3). In another preferred device, the feedstock gas is an unwanted gas to be decomposed into a desired form. Gas reactor devices of the invention can, for example, decompose gases such as CO2, CH4, or NOR.
    Type: Application
    Filed: January 7, 2015
    Publication date: May 7, 2015
    Inventors: J. Gary Eden, Sung-Jin Park, Jin Hoon Cho, Seung Hoon Sung, Min Hwan Kim
  • Publication number: 20150079587
    Abstract: Method for detecting target nucleic acids by simultaneous isothermal amplification of the target nucleic acids and a signal probe 5 using an external primer set, a DNA-RNA-DNA hybrid primer set and a DNA-RNA-DNA hybrid signal probe. The method can be used to amplify target nucleic acids in a sample, rapid and exact manner without the risk of contamination compared to the conventional methods such as PCR, and it can simultaneously amplify target nucleic acid and a signal probe, so that it can be applied to various genome projects, detection and identification of a pathogen, detection of gene modification producing a predetermined phenotype, detection of hereditary diseases or determination of sensibility to diseases, and estimation of gene expression. Thus, the method is useful for molecular biological studies and disease diagnosis.
    Type: Application
    Filed: May 14, 2013
    Publication date: March 19, 2015
    Applicant: Green Cross Medical Science Corp.
    Inventors: Min Hwan KIM, Sook LEE, Un Ok KIM, Ji Won JEONG, Joo Hee LEE
  • Patent number: 8975693
    Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, a buried layer a second conductivity type different from the first conductivity type on the substrate and an epitaxial layer of the second conductivity type on the buried layer. The device further includes a pocket well of the first conductivity type in the epitaxial layer, a first drift region in the epitaxial layer at least partially overlapping the pocket well, a second drift region in the epitaxial layer and spaced apart from the first drift region, and a body region of the first conductivity type in the pocket well. A gate electrode is disposed on the body region, the pocket well and the first drift region and has an edge overlying the epitaxial region between the first and second drift regions.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: March 10, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eung-Kyu Lee, Jae-June Jang, Hoon Chang, Min-Hwan Kim, Sung-Ryoul Bae, Dong-Eun Jang
  • Patent number: 8968668
    Abstract: A microplasma device of the invention includes a microcavity or microchannel defined at least partially within a thick metal oxide layer consisting essentially of defect free oxide. Electrodes are arranged with respect to the microcavity or microchannel to stimulate plasma generation in said microcavity or microchannel upon application of suitable voltage and at least one of the electrodes is encapsulated within the thick metal oxide layer. Large arrays can be formed and are highly robust as lack of microcracks in the oxide avoid dielectric breakdown.
    Type: Grant
    Filed: June 20, 2012
    Date of Patent: March 3, 2015
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: J. Gary Eden, Sung-Jin Park, Jin Hoon Cho, Seung Hoon Sung, Min Hwan Kim
  • Publication number: 20150017748
    Abstract: An apparatus for manufacturing an light emitting diode (LED) package, includes: a heating unit heating an LED package array in a lead frame state in which a plurality of LED packages are installed to be set in an array on a lead frame; a testing unit testing an operational state of each of the LED packages in the LED package array by applying a voltage or a current to the LED package array heated by the heating unit; and a cutting unit cutting only an LED package determined to be a functional product or an LED package determined to be a defective product from the lead frame to remove the same according to the testing results of the testing unit.
    Type: Application
    Filed: September 30, 2014
    Publication date: January 15, 2015
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Won Soo JI, Choo Ho KIM, Sung Hoon OH, Min Hwan KIM, Beom Seok SHIN
  • Publication number: 20130344671
    Abstract: A semiconductor device comprising a substrate in which a first region and a second region are defined, a gate line which extends in a first direction and traverses the first region and the second region, a source region including a portion formed in the first region, a first part of a body region which is formed under the portion of the source region in the first region and has a first width, a first well which is formed under the first part of the body region in the first region and has a second width greater than the first width, a second part of the body region which is formed in the second region and has a third width, and a second well which is formed under the second part of the body region in the second region and has a fourth width smaller than the third width.
    Type: Application
    Filed: August 30, 2013
    Publication date: December 26, 2013
    Applicant: Samsung Electronics Co., Ltd.
    Inventor: MIN-HWAN KIM
  • Publication number: 20130341714
    Abstract: A semiconductor device includes a power metal-oxide-semiconductor (MOS) transistor including a semiconductor substrate, an impurity region on the semiconductor substrate, the impurity region having a first conductivity, a drift region in the impurity region, the drift region having the first conductivity, a body region in the impurity region adjacent to the drift region, the body region having a second conductivity different from the first conductivity, a drain extension insulating layer on the drift region, a gate insulating layer and a gate electrode sequentially stacked across a portion of the body region and a portion of the drift region, a drain extension electrode on the drain extension insulating layer, a drain region contacting a side of the drift region opposite to the body region, the drain region having the first conductivity, and a source region in the body region, the source region having the second conductivity.
    Type: Application
    Filed: June 19, 2013
    Publication date: December 26, 2013
    Inventors: Jae-june JANG, Kyu-heon CHO, Min-hwan KIM, Dong-eun JANG, Hoon CHANG
  • Publication number: 20130256794
    Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, a buried layer a second conductivity type different from the first conductivity type on the substrate and an epitaxial layer of the second conductivity type on the buried layer. The device further includes a pocket well of the first conductivity type in the epitaxial layer, a first drift region in the epitaxial layer at least partially overlapping the pocket well, a second drift region in the epitaxial layer and spaced apart from the first drift region, and a body region of the first conductivity type in the pocket well. A gate electrode is disposed on the body region, the pocket well and the first drift region and has an edge overlying the epitaxial region between the first and second drift regions.
    Type: Application
    Filed: November 21, 2012
    Publication date: October 3, 2013
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Eung-Kyu Lee, Jae-June Jang, Hoon Chang, Min-Hwan Kim, Sung-Ryoul Bae, Dong-Eun Jang
  • Patent number: 8530965
    Abstract: A semiconductor device comprising a substrate in which a first region and a second region are defined, a gate line which extends in a first direction and traverses the first region and the second region, a source region including a portion formed in the first region, a first part of a body region which is formed under the portion of the source region in the first region and has a first width, a first well which is formed under the first part of the body region in the first region and has a second width greater than the first width, a second part of the body region which is formed in the second region and has a third width, and a second well which is formed under the second part of the body region in the second region and has a fourth width smaller than the third width.
    Type: Grant
    Filed: April 17, 2012
    Date of Patent: September 10, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Min-Hwan Kim
  • Publication number: 20130071297
    Abstract: A microplasma device includes a microcavity or microchannel defined at least partially within a thick metal oxide layer consisting essentially of defect free oxide. Electrodes are arranged with respect to the microcavity or microchannel to stimulate plasma generation in said microcavity or microchannel. At least one of the electrodes is encapsulated within the thick metal oxide layer. A method of fabricating a microcavity or microchannel plasma device includes anodizing a flat or gently curved or gently sloped metal substrate to form a thick layer of metal oxide consisting essentially of nanopores that are perpendicular to the surface of the metal substrate. Material removal is conducted to remove metal oxide material to form a microcavity or microchannel in the thick layer of metal oxide.
    Type: Application
    Filed: June 20, 2012
    Publication date: March 21, 2013
    Applicant: The Board of Trustees of the University of Illinois
    Inventors: J. Gary Eden, Sung-Jin Park, Jin Hoon Cho, Seung Hoon Sung, Min Hwan Kim
  • Publication number: 20120299093
    Abstract: A semiconductor device comprising a substrate in which a first region and a second region are defined, a gate line which extends in a first direction and traverses the first region and the second region, a source region including a portion formed in the first region, a first part of a body region which is formed under the portion of the source region in the first region and has a first width, a first well which is formed under the first part of the body region in the first region and has a second width greater than the first width, a second part of the body region which is formed in the second region and has a third width, and a second well which is formed under the second part of the body region in the second region and has a fourth width smaller than the third width.
    Type: Application
    Filed: April 17, 2012
    Publication date: November 29, 2012
    Inventor: Min-Hwan Kim
  • Publication number: 20120286719
    Abstract: A piezoelectric element layer is further formed as a package material of a secondary battery, so that the secondary battery can be self-charged using a voltage generated in the piezoelectric element layer according to vibration generated in an electronic device and vibration generated by movement of the electronic device itself. The secondary battery includes a battery case that accommodates an electrode assembly, the battery case having an outer coating layer and a piezoelectric element layer formed on an inner surface of the outer coating layer, and a protection circuit module mounted to an outside of the battery case and electrically connected to the electrode assembly. In the secondary battery, a voltage storage is provided to the protection circuit module, and the piezoelectric element layer converts absorbed vibration into voltage and then stores the voltage in the voltage storage so that the secondary battery is self-charged as occasion demands.
    Type: Application
    Filed: May 11, 2012
    Publication date: November 15, 2012
    Applicant: Samsung SDI Co., Ltd.
    Inventors: Seol-Ah LEE, So-Ra LEE, Do-Hyung PARK, Jun-Sik KIM, Chong-Hoon LEE, Seok-Gyun WOO, Jong-Ki LEE, Min-Hwan KIM, Yoon-Chang KIM, Jake KIM
  • Patent number: 8264088
    Abstract: A semiconductor device includes a substrate having a dielectric layer and a device layer on the substrate. The device layer has an opening. First and second sublayers are disposed on the device layer and line the opening. The second sublayer serves as a stop layer for planarization to provide a substantially planarized top surface for the semiconductor device.
    Type: Grant
    Filed: July 11, 2011
    Date of Patent: September 11, 2012
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Sin Leng Lim, In Ki Kim, Jong Sung Park, Min Hwan Kim, Wei Lu
  • Publication number: 20120169129
    Abstract: An energy storage device formed by a combination of aqueous battery unit cells and non-aqueous battery unit cells is provided. The energy storage device comprises a first energy storage module formed by connecting at least one of aqueous battery unit cells in series and a second energy storage module formed by connecting at least one of lithium ion battery unit cells in series, wherein the first energy storage module and the second energy storage module are connected in parallel, the lithium ion battery unit cell is formed of a cathode active material such as LiFePO4 (LFP) or LiMn2O4 (LMO), and a voltage of the second energy storage module is included within a predetermined margin of error with reference to a voltage of the first energy storage module.
    Type: Application
    Filed: August 15, 2011
    Publication date: July 5, 2012
    Applicant: SAMSUNG SDI CO., LTD.
    Inventors: Jun-Sik Kim, Chong-Hoon Lee, Sung-Soo Kim, Seol-Ah Lee, Seok-Gyun Woo, So-Ra Lee, Jake Kim, Min-Hwan Kim, Do-Hyung Park, Jong-Ki Lee, Yoon-Chang Kim
  • Publication number: 20120122250
    Abstract: An apparatus for manufacturing an light emitting diode (LED) package, includes: a heating unit heating an LED package array in a lead frame state in which a plurality of LED packages are installed to be set in an array on a lead frame; a testing unit testing an operational state of each of the LED packages in the LED package array by applying a voltage or a current to the LED package array heated by the heating unit; and a cutting unit cutting only an LED package determined to be a functional product or an LED package determined to be a defective product from the lead frame to remove the same according to the testing results of the testing unit.
    Type: Application
    Filed: October 21, 2011
    Publication date: May 17, 2012
    Applicant: SAMSUNG LED CO., LTD.
    Inventors: Won Soo JI, Choo Ho KIM, Sung Hoon OH, Min Hwan KIM, Beom Seok SHIN
  • Publication number: 20110266688
    Abstract: A semiconductor device includes a substrate having a dielectric layer and a device layer on the substrate. The device layer has an opening. First and second sublayers are disposed on the device layer and line the opening. The second sublayer serves as a stop layer for planarization to provide a substantially planarized top surface for the semiconductor device.
    Type: Application
    Filed: July 11, 2011
    Publication date: November 3, 2011
    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Sin Leng LIM, In Ki KIM, Jong Sung PARK, Min Hwan KIM, Wei LU
  • Patent number: 7998831
    Abstract: A semiconductor device includes a substrate having a dielectric layer and a device layer on the substrate. The device layer has an opening. First and second sublayers are disposed on the device layer and line the opening. The second sublayer serves as a stop layer for planarization to provide a substantially planarized top surface for the semiconductor device.
    Type: Grant
    Filed: April 4, 2008
    Date of Patent: August 16, 2011
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Sin Leng Lim, In Ki Kim, Jong Sung Park, Min Hwan Kim, Wei Lu
  • Publication number: 20100311058
    Abstract: The present invention relates to a method for detecting target nucleic acids by simultaneous isothermal amplification of the target nucleic acids and a signal probe 5 using an external primer set, a DNA-RNA-DNA hybrid primer set and a DNA-RNA-DNA hybrid signal probe. The method according to the present invention can be used to amplify target nucleic acids in a sample, rapid and exact manner without the risk of contamination compared to the conventional methods such as PCR, and it can simultaneously amplify target nucleic acid and a signal probe, so that it can 0 be applied to various genome projects, detection and identification of a pathogen, detection of gene modification producing a predetermined phenotype, detection of hereditary diseases or determination of sensibility to diseases, and estimation of gene expression. Thus, it is useful for molecular biological studies and disease diagnosis.
    Type: Application
    Filed: April 24, 2008
    Publication date: December 9, 2010
    Applicant: RAPLEGENE INC.
    Inventors: Min Hwan Kim, Sook Lee, Un Ok Kim, Ji Won Jeong, Joo Hee Lee
  • Publication number: 20090252277
    Abstract: An upper plenum structure of a cooled pressure vessel for a prismatic very high temperature reactor which secures a space for coolant to supply to a core and also supports an upper reflector located inside a graphite structure on top of the core. The upper plenum structure includes a cavity structure where the coolant goes down in the upper plenum structure, a plurality of upper reflector supports formed with the cavity and supporting the upper reflector located on top thereof, and a plurality of coolant distributing blocks. Each of the coolant distributing blocks is coupled with a bottom portion of a respective one of the upper reflector supports and is located on top of the core in order to distribute the coolant collected in a cavity, formed by the upper reflector support, to the core. The coolant distributing blocks cooperate with the upper reflector supports to define the cavity structure.
    Type: Application
    Filed: September 2, 2008
    Publication date: October 8, 2009
    Applicants: KOREA ATOMIC ENGERGY RESEARCH INSTITUTE, KOREA HYDRO & NUCLEAR POWER CO., LTD.
    Inventors: Min-Hwan KIM, Hong-Sik LIM, Dong-Ok KIM, Jong-Hwa CHANG, Won-Jae LEE
  • Patent number: 7596317
    Abstract: An optical network system includes a central office (CO) comprising an A-band BLS to be injected into a light source for downstream signals, an A-band BLS coupling device for coupling the A-band BLS, a first wavelength-division multiplexer/demultiplexer connected to the A-band BLS coupling device for multiplexing/demultiplexing, and a plurality of first optical transceivers connected to the first wavelength-division multiplexer/demultiplexer; a remote node (RN) comprising a B-band BLS coupling device and a second wavelength-division multiplexer/demultiplexer connected to the B-band BLS coupling device for multiplexing/demultiplexing, and being connected to the CO through an optical fiber; and a plurality of optical network terminations (ONTs) including a plurality of second optical transceivers connected to the second wavelength-division multiplexer/demultiplexer, wherein either the RN or one of the plurality of ONTs further includes a B-band BLS to be injected to a light source for upstream signals.
    Type: Grant
    Filed: May 10, 2007
    Date of Patent: September 29, 2009
    Assignee: Korea Advanced Institute of Science and Technology
    Inventors: Chang-Hee Lee, Sang-Mook Lee, Min-Hwan Kim