Patents by Inventor Min Ki Ryu
Min Ki Ryu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11927778Abstract: The present invention relates to a variable light transmittance element including a variable light transmittance structure, wherein the variable light transmittance structure includes: a first electrode; a variable light transmittance layer made of a transparent semiconductor material in which metal nanoparticles are dispersed, and electrically connected to the first electrode; a second electrode; and an insulating layer interposed between the variable light transmittance layer and the second electrode, and also relates to a color filter for a display device and smart window including the same.Type: GrantFiled: November 15, 2019Date of Patent: March 12, 2024Assignee: RMK INC.Inventor: Min Ki Ryu
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Publication number: 20230042988Abstract: A vertical-structure field-effect transistor comprises: a gate electrode, which is formed on a substrate and has a horizontal plane extending in the planar direction and a vertical plane extending in the height direction; a gate insulating layer for covering the gate electrode; a vertical channel which is formed on the gate insulating layer and has a channel formed in the height direction; a source electrode formed to make contact with one end of the vertical channel; and a drain electrode formed to make contact with the other end of the vertical channel and formed at a height level different from that of the source electrode, wherein channel on/off of the vertical channel is controlled by means of an electric field formed from the vertical plane of the gate electrode to the vertical channel, and the source electrode and/or the drain electrode can be non-overlapping on the gate electrode in the height direction of the gate electrode.Type: ApplicationFiled: October 12, 2022Publication date: February 9, 2023Applicant: KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION, SEJONG CAMPUSInventors: Mon Pyo HONG, Min Ki RYU
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Publication number: 20220026606Abstract: The present invention relates to a variable light transmittance element including a variable light transmittance structure, wherein the variable light transmittance structure includes: a first electrode; a variable light transmittance layer made of a transparent semiconductor material in which metal nanoparticles are dispersed, and electrically connected to the first electrode; a second electrode; and an insulating layer interposed between the variable light transmittance layer and the second electrode, and also relates to a color filter for a display device and smart window including the same.Type: ApplicationFiled: November 15, 2019Publication date: January 27, 2022Inventor: Min Ki RYU
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Publication number: 20200158205Abstract: A damper for an engine mounted with a motor includes a first rotating body directly connected with an end portion of a crankshaft, a rotor constituting the motor and being integrally mounted at the first rotating body, a second rotating body installed at an inner side of the first rotating body to be rotatable relative to the first rotating body, and a first damper spring, a second damper spring and a third damper spring installed to be elastically deformed along a circumference direction between the first rotating body and the second rotating body. The first damper spring, the second damper spring and the third damper spring are all disposed within the length along the axial direction of the motor.Type: ApplicationFiled: February 20, 2019Publication date: May 21, 2020Inventors: Jong Won Lee, Kyoung Pyo Ha, Min Ki Ryu
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Patent number: 9628079Abstract: A level shifter circuit a first transistor connected between a power source terminal of the level shifter circuit and an output terminal of the level shifter circuit, the first transistor being configured to transmit, in response to a first signal and a second signal, a power source voltage applied from the power source terminal to the output terminal, the first signal being received from an input terminal of the level shifter circuit through a first gate of the first transistor, the second signal being received through a second gate of the first transistor, and a second transistor connected between a ground terminal of the level shifter circuit and the output terminal, the second transistor being configured to transmit a ground voltage from the ground terminal to the output terminal in response to a gate signal received through a gate of the second transistor.Type: GrantFiled: February 22, 2016Date of Patent: April 18, 2017Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Jae-Eun Pi, Chunwon Byun, OhSang Kwon, Eunsuk Park, Min Ki Ryu, Chi-Sun Hwang
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Publication number: 20160248426Abstract: A level shifter circuit a first transistor connected between a power source terminal of the level shifter circuit and an output terminal of the level shifter circuit, the first transistor being configured to transmit, in response to a first signal and a second signal, a power source voltage applied from the power source terminal to the output terminal, the first signal being received from an input terminal of the level shifter circuit through a first gate of the first transistor, the second signal being received through a second gate of the first transistor, and a second transistor connected between a ground terminal of the level shifter circuit and the output terminal, the second transistor being configured to transmit a ground voltage from the ground terminal to the output terminal in response to a gate signal received through a gate of the second transistor.Type: ApplicationFiled: February 22, 2016Publication date: August 25, 2016Inventors: Jae-Eun PI, Chunwon BYUN, OhSang KWON, Eunsuk PARK, Min Ki RYU, Chi-Sun HWANG
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Publication number: 20160240563Abstract: Provided is a semiconductor device. The semiconductor device includes a second semiconductor pattern disposed on the substrate and configured to provide a channel region, and a first semiconductor pattern disposed between the substrate and the second semiconductor pattern, wherein the first semiconductor pattern includes a channel region that is a portion in contact with the second semiconductor pattern and source/drain regions that are portions exposed by the second semiconductor pattern.Type: ApplicationFiled: February 12, 2016Publication date: August 18, 2016Inventors: Sang-Hee PARK, Chi-Sun HWANG, Min Ki RYU, Jae-Eun PI, Jong-Beom KO, Hyein YEOM
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Patent number: 9263592Abstract: A transistor includes source/drain electrodes provided on a substrate; a semiconductor oxide layer provided between the source/drain electrodes; a gate electrode facing the semiconductor oxide layer; and a gate insulating layer interposed between the semiconductor oxide layer and the gate electrode, wherein the semiconductor oxide layer has a nano-layered structure including at least one first nano layer comprised of a first material and at least one second nano layer comprised of a second material that are alternatingly stacked one on another to provide at least one interface, and wherein the first material and the second material are different materials that are effective to form an electron transfer channel layer at the interface.Type: GrantFiled: September 6, 2013Date of Patent: February 16, 2016Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Su Jae Lee, Chi-Sun Hwang, Hye Yong Chu, Sang Chul Lim, Jae-Eun Pi, Min Ki Ryu
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Publication number: 20150171833Abstract: Provided is a gate driver circuit. The gate driver circuit includes a plurality of sequentially connected stages, and each of stages includes an input unit including two input transistors forming diode connection, a pull-up unit including a pull-up transistor and a bootstrap capacitor, and first and second pull-down units each including two transistors. According to embodiments, an input capacitor is further included which is connected to a node between the input unit and the pull-up unit. In addition, a carry unit is further included which is connected to an output terminal and formed to transmit an output signal in a high state or a low state to a next stage.Type: ApplicationFiled: July 18, 2014Publication date: June 18, 2015Applicants: Electronics and Telecommunications Research Institute, Konkuk University Industrial Cooperation CorpInventors: Jae-Eun PI, Sang-Hee PARK, Min Ki RYU, Chi-Sun HWANG, OhSang KWON, Eunsuk PARK, Kee-Chan PARK, YeonKyung KIM
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Patent number: 9035688Abstract: Provided is a single input level shifter. The single input level shifter includes: an input unit applying a power voltage to a first node in response to an input signal and applying the input signal to a second node in response to a reference signal; a bootstrapping unit applying the power voltage to the second node according to a voltage level of the first node; and an output unit applying the input signal to an output terminal in response to the reference signal and applying the power voltage to the output terminal according to the voltage level of the first node, wherein the bootstrapping unit includes a capacitor between the first and second nodes, and when the input signal is shifted from a first voltage level to a second voltage level, the bootstrapping unit raises the voltage level of the first node to a level higher than the power voltage.Type: GrantFiled: August 27, 2013Date of Patent: May 19, 2015Assignees: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE, KONKUK UNIVERSITY INDUSTRIAL COOPERATION CORP.Inventors: Jae-Eun Pi, Kee-Chan Park, Sangyeon Kim, Joondong Kim, Yeon Kyung Kim, HongKyun Lym, Sang-Hee Park, Byoung Gon Yu, Chi-Sun Hwang, Jong Woo Kim, OhSang Kwon, Min Ki Ryu
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Patent number: 8841665Abstract: Disclosed is a method for manufacturing an oxide thin film transistor, including: forming a gate electrode on a substrate on which a buffer layer is formed; forming a gate insulation layer on an entire surface of the substrate on which the gate electrode is formed; forming an oxide semiconductor layer on the gate insulation layer; forming a first etch stop layer on the oxide semiconductor layer; forming a second etch stop layer on the first etch stop layer by an atomic layer deposition method; patterning the first etch stop layer and the second etch stop layer, or forming a contact hole, through which a part of the oxide semiconductor layer is exposed, in the first etch stop layer and the second etch stop layer; forming a source electrode and a drain electrode on the first etch stop layer and the second etch stop layer; and forming a passivation layer on the entire surface of the substrate on which the source electrode and the drain electrode are formed.Type: GrantFiled: March 22, 2013Date of Patent: September 23, 2014Assignee: Electronics and Telecommunications Research InstituteInventors: Sang Hee Park, Min Ki Ryu, Him Chan Oh, Chi Sun Hwang
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Publication number: 20140159036Abstract: According to example embodiments of the inventive concept, provided is a transistor with a nano-layered oxide semiconductor layer. The oxide semiconductor layer may include at least one first nano layer and at least one second nano layer that are alternatingly stacked one on another. Here, the first nano layer and the second nano layer may include different materials from each other, and thus, a channel with high electron mobility may be formed at the interface between the first and second nano layers. Accordingly, the transistor can have high reliability.Type: ApplicationFiled: September 6, 2013Publication date: June 12, 2014Applicant: Electronics and Telecommunications Research InstituteInventors: Su Jae LEE, Chi-Sun HWANG, Hye Yong CHU, Sang Chul LIM, Jae-Eun PI, Min Ki RYU
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Patent number: 8749300Abstract: Disclosed is a DC voltage conversion circuit of a liquid crystal display apparatus, including: a main pumping circuit including a plurality of thin film transistors and configured to output voltage for driving a liquid crystal display apparatus when the plurality of thin film transistors are alternately turned on or off; and a switch control signal generator configured to control voltages applied to gates of the plurality of thin film transistors by inversion of a clock signal, in which each thin film transistor is turned on when positive gate-source voltage is applied thereto, and turned off when negative gate-source voltage is applied thereto.Type: GrantFiled: October 2, 2012Date of Patent: June 10, 2014Assignees: Electronics and Telecommunications Research Institute, Konkuk University Industrial Cooperation Corp.Inventors: Jae Eun Pi, Kee Chan Park, Hong Kyun Leem, Joon Dong Kim, Youn Kyung Kim, Ji Sun Kim, Byoung Gon Yu, Sang Hee Park, Him Chan Oh, Min Ki Ryu, Chi Sun Hwang
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Publication number: 20140062572Abstract: Provided is a single input level shifter. The single input level shifter includes: an input unit applying a power voltage to a first node in response to an input signal and applying the input signal to a second node in response to a reference signal; a bootstrapping unit applying the power voltage to the second node according to a voltage level of the first node; and an output unit applying the input signal to an output terminal in response to the reference signal and applying the power voltage to the output terminal according to the voltage level of the first node, wherein the bootstrapping unit includes a capacitor between the first and second nodes, and when the input signal is shifted from a first voltage level to a second voltage level, the bootstrapping unit raises the voltage level of the first node to a level higher than the power voltage.Type: ApplicationFiled: August 27, 2013Publication date: March 6, 2014Applicants: Electronics and Telecommunications Research Institute, Konkuk University Industrial Cooperation Corp.Inventors: Jae-Eun PI, Kee-Chan PARK, Sangyeon KIM, Joondong KIM, Yeon Kyung KIM, HongKyun LYM, Sang-Hee PARK, Byoung Gon YU, Chi-Sun HWANG, Jong Woo KIM, OhSang KWON, Min Ki RYU
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Patent number: 8546198Abstract: A method of manufacturing a transparent transistor including a substrate, source and drain electrodes formed on the substrate, each having a multi-layered structure of a lower transparent layer, a metal layer and an upper transparent layer, a channel formed between the source and drain electrodes, and a gate electrode aligned with the channel. The lower transparent layer or the upper transparent layer is formed of a transparent semiconductor layer, which is the same as the channel.Type: GrantFiled: March 11, 2013Date of Patent: October 1, 2013Assignee: Electronics and Telecommunications Research InstituteInventors: Min Ki Ryu, Chi Sun Hwang, Chun Won Byun, Hye Yong Chu, Kyoung Ik Cho
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Patent number: 8546199Abstract: A method of manufacturing a transparent transistor including a substrate, source and drain electrodes formed on the substrate, each having a multi-layered structure of a lower transparent layer, a metal layer and an upper transparent layer, a channel formed between the source and drain electrodes, and a gate electrode aligned with the channel. The lower transparent layer or the upper transparent layer is formed of a transparent semiconductor layer, which is the same as the channel.Type: GrantFiled: March 11, 2013Date of Patent: October 1, 2013Assignee: Electronics and Telecommunications Research InstituteInventors: Min Ki Ryu, Chi Sun Hwang, Chun Won Byun, Hye Yong Chu, Kyoung Ik Cho
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Patent number: 8493768Abstract: Provided is a memory cell including: a ferroelectric transistor; a plurality of switching elements electrically connected to the ferroelectric transistor; and a plurality of control lines for transmitting individual control signals to each of the plurality of switching element for separately controlling the plurality of switching elements. The plurality of switching elements are configured to be separately controlled on the basis of the individual control signals so as to prevent each electrode of the ferroelectric transistor from being floated.Type: GrantFiled: November 21, 2011Date of Patent: July 23, 2013Assignee: Electronics and Telecommunications Research InstituteInventors: Chunwon Byun, ByeongHoon Kim, Sung Min Yoon, Shinhyuk Yang, Min Ki Ryu, Chi-Sun Hwang, Sang-Hee Park, Kyoung Ik Cho
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Patent number: 8409935Abstract: A method of manufacturing a transparent transistor including a substrate, source and drain electrodes formed on the substrate, each having a multi-layered structure of a lower transparent layer, a metal layer and an upper transparent layer, a channel formed between the source and drain electrodes, and a gate electrode aligned with the channel. The lower transparent layer or the upper transparent layer is formed of a transparent semiconductor layer, which is the same as the channel.Type: GrantFiled: August 21, 2012Date of Patent: April 2, 2013Assignee: Electronics and Telcommunications Research InstituteInventors: Min Ki Ryu, Chi Sun Hwang, Chun Won Byun, Hye Yong Chu, Kyoung Ik Cho
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Publication number: 20120315729Abstract: A method of manufacturing a transparent transistor including a substrate, source and drain electrodes formed on the substrate, each having a multi-layered structure of a lower transparent layer, a metal layer and an upper transparent layer, a channel formed between the source and drain electrodes, and a gate electrode aligned with the channel. The lower transparent layer or the upper transparent layer is formed of a transparent semiconductor layer, which is the same as the channel.Type: ApplicationFiled: August 21, 2012Publication date: December 13, 2012Applicant: Electronics and Telecommunications Research InstituteInventors: Min Ki RYU, Chi Sun Hwang, Chun Won Byun, Hye Yong Chu, Kyoung Ik Cho
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Publication number: 20120286271Abstract: Disclosed are an oxide thin film transistor resistant to light and bias stress, and a method of manufacturing the same. The method includes forming a gate electrode on a substrate; forming a gate insulating layer on an upper part including the gate electrode; forming a source electrode and a drain electrode on the insulating layer; forming an active layer insulated from the gate electrode by the gate insulating layer and formed of an oxide semiconductor and a diffusion barrier film; and forming a protective layer on a portion of the source electrode and drain electrode and the upper part including the active layer, wherein the diffusion barrier film reduces movement of holes and prevents ionized oxygen vacancies from being diffused.Type: ApplicationFiled: May 9, 2012Publication date: November 15, 2012Inventors: Him Chan OH, Sang Hee Park, Chi Sun Hwang, Min Ki Ryu