Patents by Inventor Min Ki Ryu
Min Ki Ryu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8269220Abstract: Provided is a transparent transistor including a substrate, source and drain electrodes formed on the substrate, each having a multi-layered structure of a lower transparent layer, a metal layer and an upper transparent layer, a channel formed between the source and drain electrodes, and a gate electrode aligned with the channel. Here, the lower transparent layer or the upper transparent layer is formed of a transparent semiconductor layer, which is the same as the channel. Thus, the use of the multi-layered transparent conductive layer can ensure transparency and conductivity, overcome a problem of contact resistance between the source and drain electrodes and a semiconductor, and improve processibility by patterning the multi-layered transparent conductive layer all at once, while deposition is performed layer by layer.Type: GrantFiled: September 4, 2009Date of Patent: September 18, 2012Assignee: Electronics and Telecommunications Research InstituteInventors: Min Ki Ryu, Chi Sun Hwang, Chun Won Byun, Hye Yong Chu, Kyoung Ik Cho
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Publication number: 20120134197Abstract: Provided is a memory cell including: a ferroelectric transistor; a plurality of switching elements electrically connected to the ferroelectric transistor; and a plurality of control lines for transmitting individual control signals to each of the plurality of switching element for separately controlling the plurality of switching elements. The plurality of switching elements are configured to be separately controlled on the basis of the individual control signals so as to prevent each electrode of the ferroelectric transistor from being floated.Type: ApplicationFiled: November 21, 2011Publication date: May 31, 2012Applicant: ELETRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Chunwon Byun, ByeongHoon Kim, Sung Min Yoon, Shinhyuk Yang, Min Ki Ryu, Chi-Sun Hwang, Sang-Hee Park, Kyoung Ik Cho
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Publication number: 20120007158Abstract: Provided is a non-volatile memory transistor having a double gate structure, including a first gate electrode formed on a substrate and to which an operating voltage is applied, a first gate insulating layer formed on the first gate electrode, source and drain electrodes formed on the first gate insulating layer at predetermined intervals, a channel layer formed on the first gate insulating layer between the source and drain electrodes, a second gate insulating layer formed on the channel layer, and a second gate electrode formed on the second gate insulating layer and connected to the first gate electrode such that the operating voltage is applied thereto. Accordingly, a turn-on voltage of the memory transistor can be easily controlled.Type: ApplicationFiled: June 30, 2011Publication date: January 12, 2012Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Sung Min YOON, Shin Hyuk Yang, Chun Won Byun, Min Ki Ryu, Soon Won Jung
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Patent number: 8095343Abstract: Provided are a method and apparatus for modeling source-drain current of a TFT. The method includes receiving sample data, the sample data including a sample input value and a sample output value; adjusting modeling variables according to the sample data; calculating a current model value according to the adjusted modeling variables; when a difference between the calculated current model value and the sample output value is smaller than a predetermined threshold value, fitting a current model by applying the adjusted modeling variables to the current model; applying actual input data to the fitted current model; and outputting a result value corresponding to the actual input data, wherein the current model is a model for predicting the source-drain current of the TFT.Type: GrantFiled: August 29, 2008Date of Patent: January 10, 2012Assignee: Electronics and Telecommunications Research InstituteInventors: Jae Heon Shin, Chi Sun Hwang, Min Ki Ryu, Woo Seok Cheong, Hye Yong Chu
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Publication number: 20110305062Abstract: Provided are a memory cell and a memory device using the same, particularly, a nonvolatile non-destructive readable random access memory cell including a ferroelectric transistor as a storage unit and a memory device using the same. The memory cell includes a ferroelectric transistor having a drain to which a reference voltage is applied, a first switch configured to allow a source of the ferroelectric transistor to be connected to a first line in response to a scan signal, and a second switch configured to allow a gate of the ferroelectric transistor to be connected to a second line in response to the scan signal. The memory device enables random access and performs non-destructive read-out (NDRO) operations.Type: ApplicationFiled: September 21, 2010Publication date: December 15, 2011Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Chun Won BYUN, Byeong Hoon Kim, Sung Min Yoon, Kyoung Ik Cho, Sang Hee Park, Chi Sun Hwang, Min Ki Ryu, Shin Hyuk Yang, Oh Sang Kwon, Eun Suk Park
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Patent number: 8071434Abstract: Provided is a method of fabricating a thin film transistor including source and drain electrodes, a novel channel layer, a gate insulating layer, and a gate electrode, which are formed on a substrate. The method includes the steps of forming the channel layer using an oxide semiconductor doped with boron; and patterning the channel layer. The channel layer formed is an oxide semiconductor thin film doped with boron. The electrical characteristics and high temperature stability of the thin film transistor are improved remarkably.Type: GrantFiled: September 16, 2009Date of Patent: December 6, 2011Assignee: Electronics and Telecommunications Research InstituteInventors: Woo Seok Cheong, Sung Mook Chung, Min Ki Ryu, Chi Sun Hwang, Hye Yong Chu
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Publication number: 20110266542Abstract: Provided are a semiconductor device including a dual gate transistor and a method of fabricating the same. The semiconductor device includes a lower gate electrode, an upper gate electrode on the lower gate electrode, a contact plug interposed between the lower gate electrode and the upper gate electrode, and connecting the lower gate electrode to the upper gate electrode, and a functional electrode spaced apart from the upper gate electrode and formed at the same height as the upper gate electrode. The dual gate transistor exhibiting high field effect mobility is applied to the semiconductor device, so that characteristics of the semiconductor device can be improved. In particular, since no additional mask or deposition process is necessary, a large-area high-definition semiconductor device can be mass-produced with neither an increase in process cost nor a decrease in yield.Type: ApplicationFiled: April 27, 2011Publication date: November 3, 2011Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Min Ki RYU, Sang Hee Park, Chi Sun Hwang, Kyoung Ik Cho
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Publication number: 20110249202Abstract: A power reduction television with a photo frame is provided. The power reduction television includes a first display configured to display a first video image, a low power second display configured to display a second video image, and a display control unit configured to control the second display to display the second video image, when the first video image is not displayed through the first display.Type: ApplicationFiled: April 6, 2011Publication date: October 13, 2011Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Sang Hee PARK, Chi Sun Hwang, Min Ki Ryu
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Publication number: 20110212612Abstract: A memory device including a dielectric thin film having a plurality of dielectric layers and a method of manufacturing the same are provided. The memory device includes: a bottom electrode; at least one dielectric thin film disposed on the bottom electrode and having a plurality of dielectric layers with different charge trap densities from each other; and an top electrode disposed on the dielectric thin film. Therefore, a memory device, which can be readily manufactured by a simple process and can be highly integrated using its simple structure, can be provided.Type: ApplicationFiled: May 5, 2011Publication date: September 1, 2011Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Sung-Yool CHOI, Min Ki RYU, Ansoon KIM, Chil Seong AH, Han Young YU
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Patent number: 7960774Abstract: A memory device including a dielectric thin film having a plurality of dielectric layers and a method of manufacturing the same are provided. The memory device includes: a bottom electrode; at least one dielectric thin film disposed on the bottom electrode and having a plurality of dielectric layers with different charge trap densities from each other; and an top electrode disposed on the dielectric thin film. Therefore, a memory device, which can be readily manufactured by a simple process and can be highly integrated using its simple structure, can be provided.Type: GrantFiled: December 1, 2006Date of Patent: June 14, 2011Assignee: Electronics and Telecommunications Research InstituteInventors: Sung-Yool Choi, Min Ki Ryu, Ansoon Kim, Chil Seong Ah, Han Young Yu
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Publication number: 20100258437Abstract: Provided is a reactive sputtering apparatus, and more particularly, a reactive sputtering apparatus capable of effectively ionizing a reactive gas using inductively coupled plasma (ICP). The reactive sputtering apparatus includes: a chamber having an inlet port for introducing a plasma gas thereinto and an outlet port for exhausting the gas used during reactive sputtering to the exterior; an ICP generator disposed on the chamber, ionizing a reactive gas, and injecting the ionized gas into the chamber; and at least one sputter gun located at a side surface of the chamber and supporting a target. Therefore, the reactive sputtering apparatus can improve an ionization rate of a reactive gas using inductively coupled plasma to reduce a process temperature and improve uniformity and step coverage of thin film deposition at low cost.Type: ApplicationFiled: September 2, 2008Publication date: October 14, 2010Inventors: Woo Seok Cheong, Chi Sun Hwang, Min Ki Ryu
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Publication number: 20100155716Abstract: Provided are a thin film transistor, to which a boron-doped oxide semiconductor thin film is applied as a channel layer, and a method of fabricating the same. The thin film transistor includes source and drain electrodes, a channel layer, a gate insulating layer, and a gate electrode, which are formed on a substrate. The channel layer is an oxide semiconductor thin film doped with boron. Therefore, it is possible to remarkably improve electrical characteristics and high temperature stability of the thin film transistor.Type: ApplicationFiled: September 16, 2009Publication date: June 24, 2010Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Woo Seok CHEONG, Sung Mook CHUNG, Min Ki RYU, Chi Sun HWANG, Hye Yong CHU
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Publication number: 20100155792Abstract: Provided is a transparent transistor including a substrate, source and drain electrodes formed on the substrate, each having a multi-layered structure of a lower transparent layer, a metal layer and an upper transparent layer, a channel formed between the source and drain electrodes, and a gate electrode aligned with the channel. Here, the lower transparent layer or the upper transparent layer is formed of a transparent semiconductor layer, which is the same as the channel. Thus, the use of the multi-layered transparent conductive layer can ensure transparency and conductivity, overcome a problem of contact resistance between the source and drain electrodes and a semiconductor, and improve processibility by patterning the multi-layered transparent conductive layer all at once, while deposition is performed layer by layer.Type: ApplicationFiled: September 4, 2009Publication date: June 24, 2010Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Min Ki Ryu, Chi Sun Hwang, Chun Won Byun, Hye Yong Chu, Kyong Ik Cho
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Publication number: 20100065803Abstract: Provided is a resistance variable non-volatile memory device using a trap-controlled Space Charge Limited Current (SCLC), and a manufacturing method thereof. The memory device includes a bottom electrode; an inter-electrode dielectric thin film diffusion prevention film formed on the bottom electrode; a dielectric thin film formed on the inter-electrode dielectric thin film diffusion prevention film and having a plurality of layers with different charge trap densities; and a top electrode formed on the dielectric thin film.Type: ApplicationFiled: November 28, 2007Publication date: March 18, 2010Applicant: Electronics and Telecommunications Research InstituteInventors: Sung-Yool Choi, Min-Ki Ryu, Hu-Young Jeong
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Publication number: 20100006837Abstract: Provided are a composition for an oxide semiconductor thin film, a field effect transistor using the same and a method of fabricating the field effect transistor. The composition includes an aluminum oxide, a zinc oxide, an indium oxide and a tin oxide. The thin film formed of the composition is in amorphous phase. The field effect transistor having an active layer formed of the composition can have an improved electrical characteristic and be fabricated by a low temperature process.Type: ApplicationFiled: July 1, 2009Publication date: January 14, 2010Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Doo Hee Cho, Sang Hee Park, Chi Sun Hwang, Hye Yong Chu, Kyoung Ik Cho, Shin Hyuk Yang, Chun Won Byun, Eun Suk Park, Oh Sang Kwon, Min Ki Ryu, Jae Heon Shin, Woo Seok Cheong, Sung Mook Chung, Jeong Ik Lee
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Publication number: 20090157372Abstract: Provided are a method and apparatus for modeling source-drain current of a TFT. The method includes receiving sample data, the sample data including a sample input value and a sample output value; adjusting modeling variables according to the sample data; calculating a current model value according to the adjusted modeling variables; when a difference between the calculated current model value and the sample output value is smaller than a predetermined threshold value, fitting a current model by applying the adjusted modeling variables to the current model; applying actual input data to the fitted current model; and outputting a result value corresponding to the actual input data, wherein the current model is a model for predicting the source-drain current of the TFT.Type: ApplicationFiled: August 29, 2008Publication date: June 18, 2009Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Jae Heon SHIN, Chi Sun Hwang, Min Ki Ryu, Woo Seok Cheong, Hye Yong Chu
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Patent number: 7537883Abstract: Provided is a method of manufacturing a nano size-gap electrode device. The method includes the steps of: disposing a floated nano structure on a semiconductor layer; forming a mask layer having at least one opening pattern to intersect the nano structure; and depositing a metal on the semiconductor layer exposed through the opening pattern to form an electrode, such that a nano size-gap is provided under the nano structure by the nano structure.Type: GrantFiled: June 6, 2006Date of Patent: May 26, 2009Assignee: Electronics and Telecommunications Research InstituteInventors: Han Young Yu, In Bok Baek, Chang Geun Ahn, Ki Ju Im, Jong Heon Yang, Ung Hwan Pi, Min Ki Ryu, Chan Woo Park, Sung Yool Choi, Seong Jae Lee
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Publication number: 20070126045Abstract: A memory device including a dielectric thin film having a plurality of dielectric layers and a method of manufacturing the same are provided. The memory device includes: a bottom electrode; at least one dielectric thin film disposed on the bottom electrode and having a plurality of dielectric layers with different charge trap densities from each other; and an top electrode disposed on the dielectric thin film. Therefore, a memory device, which can be readily manufactured by a simple process and can be highly integrated using its simple structure, can be provided.Type: ApplicationFiled: December 1, 2006Publication date: June 7, 2007Inventors: Sung-Yool Choi, Min Ki Ryu, Ansoon Kim, Chil Seong Ah, Han Young Yu
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Publication number: 20070126001Abstract: An organic semiconductor device and a method of fabricating the same are provided. The device includes: a first electrode; an electron channel layer formed on the first electrode; and a second electrode formed on the electron channel layer, wherein the electron channel layer comprises: a lower organic layer formed on the first electrode; a nano-particle layer formed on the lower organic layer and including predetermined sizes of nano-particles that are spaced a predetermined distance apart from each other; and an upper organic layer formed over the nano-particle layer. Accordingly, a highly integrated organic semiconductor device can be fabricated by a simple fabrication process, and nonuniformity of devices due to threshold voltage characteristics and downsizing of the device can resolved, so that a semiconductor device having excellent performance can be implemented.Type: ApplicationFiled: August 1, 2006Publication date: June 7, 2007Inventors: Sung-Yool Choi, Min Ki Ryu, Ansoon Kim, Chil Seong Ah, Han Young Yu
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Publication number: 20070072336Abstract: Provided is a method of manufacturing a nano size-gap electrode device. The method includes the steps of: disposing a floated nano structure on a semiconductor layer; forming a mask layer having at least one opening pattern to intersect the nano structure; and depositing a metal on the semiconductor layer exposed through the opening pattern to form an electrode, such that a nano size-gap is provided under the nano structure by the nano structure.Type: ApplicationFiled: June 6, 2006Publication date: March 29, 2007Inventors: Han Young Yu, In Bok Baek, Chang Geun Ahn, Ki Ju Im, Jong Heon Yang, Ung Hwan Pi, Min Ki Ryu, Chan Woo Park, Sung Yool Choi, Seong Jae Lee