Abstract: A pixel includes an organic light emitting diode (OLED), a pixel circuit, and first and second transistors. The OLD includes a cathode electrode connected to a second power source. The pixel circuit includes a driving transistor having a gate electrode initialized by a third power source. The driving transistor controls the amount of current flowing from a first power source to the second power source via the OLED. The first transistor is connected between a fourth power source and the second power source and an anode electrode of the OLED. The first transistor is turned on based on a scan signal is supplied to a scan line. The second transistor is connected between a data line and the pixel circuit. The second transistor is turned on when the scan signal is supplied to the ith scan line.

Abstract: The present invention relates to a method of determining a company related to news based on scoring and an apparatus for performing the method. A method of determining a company related to news based on scoring, comprises determining, by a news ticker mapping apparatus, a candidate ticker for a sentence and determining, by the news ticker mapping apparatus, a sentence ticker for the sentence on the basis of a candidate ticker score, which is a score for the candidate ticker.

Abstract: The present invention relates to a method of determining a candidate company related to news and an apparatus for performing the method. The method of determining a candidate company related to news, comprises determining, by a news ticker mapping apparatus, an entity name for news and determining, by the news ticker mapping apparatus, a candidate ticker on the basis of the entity name.

Abstract: The present invention relates to a method of determining a news ticker related to news based on a sentence ticker and an apparatus for performing the method. The method of determining a news ticker related to news based on a sentence ticker, comprises determining, by a news ticker mapping apparatus, each of a plurality of sentences tickers for each of a plurality of sentences, determining, by the news ticker mapping apparatus, a weight for each of the plurality of sentences tickers and determining, by the news ticker mapping apparatus, the news ticker on the basis of the plurality of sentences tickers and the weight for each of the plurality of sentences tickers.

Abstract: Provided herein is a memory device and a method of operating the same. The memory device may include a plurality of memory cells, a peripheral circuit, and a control logic. The peripheral circuit may be configured to perform a plurality of program loops, each including a program pulse apply operation and a program verify operation, on selected memory cells of the plurality of memory cells. The control logic may be configured to control, in response to a suspend command, the peripheral circuit to suspend an n-th program loop of the plurality of program loops, where n is a natural number of 1 or more, and configured to control, in response to a resume command, the peripheral circuit to resume the suspended n-th program loop after performing a recovery pulse apply operation compensating for charges detrapped from a channel area of the selected memory cells.

Abstract: Provided herein is a memory device and a method of operating the same. The memory device may include a plurality of memory cells, a peripheral circuit, and a control logic. The peripheral circuit may be configured to perform a plurality of program loops, each including a program pulse apply operation and a program verify operation, on selected memory cells of the plurality of memory cells. The control logic may be configured to control, in response to a suspend command, the peripheral circuit to suspend an n-th program loop of the plurality of program loops, where n is a natural number of 1 or more, and configured to control, in response to a resume command, the peripheral circuit to resume the suspended n-th program loop after performing a recovery pulse apply operation compensating for charges detrapped from a channel area of the selected memory cells.

Abstract: A semiconductor device includes a memory string coupled between a common source line and a bit line, the memory string including at least one first selection transistor, a plurality of memory cells, and a plurality of second selection transistors. The semiconductor device also includes selection lines respectively coupled to the second selection transistors. The semiconductor device further includes a control logic circuit configured to float a first group of selection lines from among the selection lines at a first time and configured to float a second group of selection lines from among the selection lines at a second time different from the first time.

Abstract: The invention is directed to an electronic device. A memory device having improved reliability according to an embodiment includes a memory cell array including a plurality of memory cells, a peripheral circuit performing a program operation on selected memory cells, among the plurality of memory cells, and a control logic controlling the peripheral circuit to perform an additional program operation on memory cells corresponding to a deep erased state where the memory cells has a threshold voltage having a lower voltage level than a threshold voltage of an erase state, among the selected memory cells, after the program operation is completed.

Abstract: A tile-based rendering method includes receiving a drawcall, determining a location of primitives in a frame based on the drawcall, dividing the frame into a plurality of tiles, and rendering the tiles, wherein the rendering includes determining a rendering order of the tiles based on primitives included in the tiles, and rendering the tiles according to the rendering order. A graphics processing unit (GPU) is configured to perform the tile-based rendering method, and may include a memory, a processor including at least one core and at least one cache. The GPU may execute a tile-based graphics pipeline for tile-based rendering of images, and allocate tiles including identical primitives to a core.

Abstract: The invention is directed to an electronic device. A memory device having improved reliability according to an embodiment includes a memory cell array including a plurality of memory cells, a peripheral circuit performing a program operation on selected memory cells, among the plurality of memory cells, and a control logic controlling the peripheral circuit to perform an additional program operation on memory cells corresponding to a deep erased state where the memory cells has a threshold voltage having a lower voltage level than a threshold voltage of an erase state, among the selected memory cells, after the program operation is completed.

Abstract: The invention is directed to an electronic device. A memory device having improved reliability according to an embodiment includes a memory cell array including a plurality of memory cells, a peripheral circuit performing a program operation on selected memory cells, among the plurality of memory cells, and a control logic controlling the peripheral circuit to perform an additional program operation on memory cells corresponding to a deep erased state where the memory cells has a threshold voltage having a lower voltage level than a threshold voltage of an erase state, among the selected memory cells, after the program operation is completed.

Abstract: A semiconductor device includes a memory string coupled between a common source line and a bit line, the memory string including at least one first selection transistor, a plurality of memory cells, and a plurality of second selection transistors. The semiconductor device also includes selection lines respectively coupled to the second selection transistors. The semiconductor device further includes a control logic circuit configured to float a first group of selection lines from among the selection lines at a first time and configured to float a second group of selection lines from among the selection lines at a second time different from the first time.

Abstract: A method of managing memory includes generating a page pool by aligning a plurality of pages of a memory; when a request to store first data is received, allocating a destination page corresponding to the first data using a page pool; and updating a page table using information about the allocated destination page.

Abstract: A method and a graphics processing apparatus for processing texture in a graphics pipeline determine a rendering level of a dynamic texture based on usage information of a target object and render the target object by texturing the target object with the dynamic texture rendered based on the rendering level. The graphics processing apparatus includes at least one cache memory, and at least one processor configured to: perform geometry processing of a dynamic texture to be mapped onto a target object, determine a rendering level of the dynamic texture based on usage information of the target object obtained by the geometry processing of the target object, render the dynamic texture based on the determined rendering level, and render the target object by texturing the target object with the rendered dynamic texture.

Abstract: An image processing method includes: determining whether a draw command that is identical to a previous draw command is input; obtaining information about a transparency of a previous frame that is performed with the previous draw command; and performing image processing on a current frame based on the information about the transparency.

Abstract: The invention is directed to an electronic device. A memory device having improved reliability according to an embodiment includes a memory cell array including a plurality of memory cells, a peripheral circuit performing a program operation on selected memory cells, among the plurality of memory cells, and a control logic controlling the peripheral circuit to perform an additional program operation on memory cells corresponding to a deep erased state where the memory cells has a threshold voltage having a lower voltage level than a threshold voltage of an erase state, among the selected memory cells, after the program operation is completed.

Abstract: A method and a graphics processing apparatus for processing texture in a graphics pipeline determine a rendering level of a dynamic texture based on usage information of a target object and render the target object by texturing the target object with the dynamic texture rendered based on the rendering level. The graphics processing apparatus includes at least one cache memory, and at least one processor configured to: perform geometry processing of a dynamic texture to be mapped onto a target object, determine a rendering level of the dynamic texture based on usage information of the target object obtained by the geometry processing of the target object, render the dynamic texture based on the determined rendering level, and render the target object by texturing the target object with the rendered dynamic texture.

Abstract: A method of managing memory includes generating a page pool by aligning a plurality of pages of a memory; when a request to store first data is received, allocating a destination page corresponding to the first data using a page pool; and updating a page table using information about the allocated destination page.

Abstract: A method of performing tile-based rendering in a graphics processing apparatus may include: generating a bitstream representing a tile binning result by performing tile binning with initial tiles having initial sizes. A determining as to whether a primitive belonging to an initial tile additionally belongs to other initial tiles bordering the initial tile is made by using the generated bitstream. A determining of a rendering tile is made, in which the rendering tile has a dynamic size and is formed by at least one of the initial tiles that the primitive belongs to, based on a result of the determining of whether the primitive additionally belongs to the other initial tiles. Rendering is performed on the primitive included in the determined rendering tile by using the determined rendering tile.

Abstract: A tile-based rendering method includes receiving a drawcall, determining a location of primitives in a frame based on the drawcall, dividing the frame into a plurality of tiles, and rendering the tiles, wherein the rendering includes determining a rendering order of the tiles based on primitives included in the tiles, and rendering the tiles according to the rendering order. A graphics processing unit (GPU) is configured to perform the tile-based rendering method, and may include a memory, a processor including at least one core and at least one cache. The GPU may execute a tile-based graphics pipeline for tile-based rendering of images, and allocate tiles including identical primitives to a core.