Patents by Inventor Min-kyu Jeong

Min-kyu Jeong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11335421
    Abstract: Provided herein is a memory device and a method of operating the same. The memory device may include a plurality of memory cells, a peripheral circuit, and a control logic. The peripheral circuit may be configured to perform a plurality of program loops, each including a program pulse apply operation and a program verify operation, on selected memory cells of the plurality of memory cells. The control logic may be configured to control, in response to a suspend command, the peripheral circuit to suspend an n-th program loop of the plurality of program loops, where n is a natural number of 1 or more, and configured to control, in response to a resume command, the peripheral circuit to resume the suspended n-th program loop after performing a recovery pulse apply operation compensating for charges detrapped from a channel area of the selected memory cells.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: May 17, 2022
    Assignee: SK hynix Inc.
    Inventor: Min Kyu Jeong
  • Publication number: 20210280262
    Abstract: Provided herein is a memory device and a method of operating the same. The memory device may include a plurality of memory cells, a peripheral circuit, and a control logic. The peripheral circuit may be configured to perform a plurality of program loops, each including a program pulse apply operation and a program verify operation, on selected memory cells of the plurality of memory cells. The control logic may be configured to control, in response to a suspend command, the peripheral circuit to suspend an n-th program loop of the plurality of program loops, where n is a natural number of 1 or more, and configured to control, in response to a resume command, the peripheral circuit to resume the suspended n-th program loop after performing a recovery pulse apply operation compensating for charges detrapped from a channel area of the selected memory cells.
    Type: Application
    Filed: August 17, 2020
    Publication date: September 9, 2021
    Inventor: Min Kyu JEONG
  • Patent number: 10847226
    Abstract: A semiconductor device includes a memory string coupled between a common source line and a bit line, the memory string including at least one first selection transistor, a plurality of memory cells, and a plurality of second selection transistors. The semiconductor device also includes selection lines respectively coupled to the second selection transistors. The semiconductor device further includes a control logic circuit configured to float a first group of selection lines from among the selection lines at a first time and configured to float a second group of selection lines from among the selection lines at a second time different from the first time.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: November 24, 2020
    Assignee: SK hynix Inc.
    Inventors: Yong Jun Kim, Gae Hun Lee, Hea Jong Yang, Chan Lim, Min Kyu Jeong
  • Patent number: 10672480
    Abstract: The invention is directed to an electronic device. A memory device having improved reliability according to an embodiment includes a memory cell array including a plurality of memory cells, a peripheral circuit performing a program operation on selected memory cells, among the plurality of memory cells, and a control logic controlling the peripheral circuit to perform an additional program operation on memory cells corresponding to a deep erased state where the memory cells has a threshold voltage having a lower voltage level than a threshold voltage of an erase state, among the selected memory cells, after the program operation is completed.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: June 2, 2020
    Assignee: SK hynix Inc.
    Inventors: Hee Youl Lee, Kyoung Cheol Kwon, Dong Hun Lee, Min Kyu Jeong, Sung Yong Chung
  • Patent number: 10553024
    Abstract: A tile-based rendering method includes receiving a drawcall, determining a location of primitives in a frame based on the drawcall, dividing the frame into a plurality of tiles, and rendering the tiles, wherein the rendering includes determining a rendering order of the tiles based on primitives included in the tiles, and rendering the tiles according to the rendering order. A graphics processing unit (GPU) is configured to perform the tile-based rendering method, and may include a memory, a processor including at least one core and at least one cache. The GPU may execute a tile-based graphics pipeline for tile-based rendering of images, and allocate tiles including identical primitives to a core.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: February 4, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Min-Kyu Jeong, Jae-Don Lee, Sang-Won Ha, Min-Young Son
  • Publication number: 20200020403
    Abstract: The invention is directed to an electronic device. A memory device having improved reliability according to an embodiment includes a memory cell array including a plurality of memory cells, a peripheral circuit performing a program operation on selected memory cells, among the plurality of memory cells, and a control logic controlling the peripheral circuit to perform an additional program operation on memory cells corresponding to a deep erased state where the memory cells has a threshold voltage having a lower voltage level than a threshold voltage of an erase state, among the selected memory cells, after the program operation is completed.
    Type: Application
    Filed: September 26, 2019
    Publication date: January 16, 2020
    Inventors: Hee Youl LEE, Kyoung Cheol KWON, Dong Hun LEE, Min Kyu JEONG, Sung Yong CHUNG
  • Patent number: 10490284
    Abstract: The invention is directed to an electronic device. A memory device having improved reliability according to an embodiment includes a memory cell array including a plurality of memory cells, a peripheral circuit performing a program operation on selected memory cells, among the plurality of memory cells, and a control logic controlling the peripheral circuit to perform an additional program operation on memory cells corresponding to a deep erased state where the memory cells has a threshold voltage having a lower voltage level than a threshold voltage of an erase state, among the selected memory cells, after the program operation is completed.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: November 26, 2019
    Assignee: SK hynix Inc.
    Inventors: Hee Youl Lee, Kyoung Cheol Kwon, Dong Hun Lee, Min Kyu Jeong, Sung Yong Chung
  • Publication number: 20190348121
    Abstract: A semiconductor device includes a memory string coupled between a common source line and a bit line, the memory string including at least one first selection transistor, a plurality of memory cells, and a plurality of second selection transistors. The semiconductor device also includes selection lines respectively coupled to the second selection transistors. The semiconductor device further includes a control logic circuit configured to float a first group of selection lines from among the selection lines at a first time and configured to float a second group of selection lines from among the selection lines at a second time different from the first time.
    Type: Application
    Filed: December 13, 2018
    Publication date: November 14, 2019
    Applicant: SK hynix Inc.
    Inventors: Yong Jun KIM, Gae Hun LEE, Hea Jong YANG, Chan LIM, Min Kyu JEONG
  • Patent number: 10380029
    Abstract: A method of managing memory includes generating a page pool by aligning a plurality of pages of a memory; when a request to store first data is received, allocating a destination page corresponding to the first data using a page pool; and updating a page table using information about the allocated destination page.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: August 13, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Don Lee, Min-Kyu Jeong, Jong-Pil Son
  • Patent number: 10331448
    Abstract: A method and a graphics processing apparatus for processing texture in a graphics pipeline determine a rendering level of a dynamic texture based on usage information of a target object and render the target object by texturing the target object with the dynamic texture rendered based on the rendering level. The graphics processing apparatus includes at least one cache memory, and at least one processor configured to: perform geometry processing of a dynamic texture to be mapped onto a target object, determine a rendering level of the dynamic texture based on usage information of the target object obtained by the geometry processing of the target object, render the dynamic texture based on the determined rendering level, and render the target object by texturing the target object with the rendered dynamic texture.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: June 25, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Min-Young Son, Kwon-Taek Kwon, Jae-Don Lee, Min-Kyu Jeong, Sang-Won Ha
  • Patent number: 10229524
    Abstract: An image processing method includes: determining whether a draw command that is identical to a previous draw command is input; obtaining information about a transparency of a previous frame that is performed with the previous draw command; and performing image processing on a current frame based on the information about the transparency.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: March 12, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min-kyu Jeong, Kwon-taek Kwon, Min-young Son, Jeong-soo Park, Sang-oak Woo
  • Publication number: 20190057744
    Abstract: The invention is directed to an electronic device. A memory device having improved reliability according to an embodiment includes a memory cell array including a plurality of memory cells, a peripheral circuit performing a program operation on selected memory cells, among the plurality of memory cells, and a control logic controlling the peripheral circuit to perform an additional program operation on memory cells corresponding to a deep erased state where the memory cells has a threshold voltage having a lower voltage level than a threshold voltage of an erase state, among the selected memory cells, after the program operation is completed.
    Type: Application
    Filed: March 20, 2018
    Publication date: February 21, 2019
    Inventors: Hee Youl LEE, Kyoung Cheol KWON, Dong Hun LEE, Min Kyu JEONG, Sung Yong CHUNG
  • Publication number: 20180150296
    Abstract: A method and a graphics processing apparatus for processing texture in a graphics pipeline determine a rendering level of a dynamic texture based on usage information of a target object and render the target object by texturing the target object with the dynamic texture rendered based on the rendering level. The graphics processing apparatus includes at least one cache memory, and at least one processor configured to: perform geometry processing of a dynamic texture to be mapped onto a target object, determine a rendering level of the dynamic texture based on usage information of the target object obtained by the geometry processing of the target object, render the dynamic texture based on the determined rendering level, and render the target object by texturing the target object with the rendered dynamic texture.
    Type: Application
    Filed: June 20, 2017
    Publication date: May 31, 2018
    Inventors: MIN-YOUNG SON, KWON-TAEK KWON, JAE-DON LEE, MIN-KYU JEONG, SANG-WON HA
  • Publication number: 20180144538
    Abstract: A method of performing tile-based rendering in a graphics processing apparatus may include: generating a bitstream representing a tile binning result by performing tile binning with initial tiles having initial sizes. A determining as to whether a primitive belonging to an initial tile additionally belongs to other initial tiles bordering the initial tile is made by using the generated bitstream. A determining of a rendering tile is made, in which the rendering tile has a dynamic size and is formed by at least one of the initial tiles that the primitive belongs to, based on a result of the determining of whether the primitive additionally belongs to the other initial tiles. Rendering is performed on the primitive included in the determined rendering tile by using the determined rendering tile.
    Type: Application
    Filed: May 26, 2017
    Publication date: May 24, 2018
    Inventors: MIN-KYU JEONG, JAE-DON LEE, KWON-TAEK KWON, MIN-YOUNG SON
  • Publication number: 20180143909
    Abstract: A method of managing memory includes generating a page pool by aligning a plurality of pages of a memory; when a request to store first data is received, allocating a destination page corresponding to the first data using a page pool; and updating a page table using information about the allocated destination page.
    Type: Application
    Filed: June 27, 2017
    Publication date: May 24, 2018
    Inventors: Jae-Don Lee, Min-Kyu Jeong, Jong-Pil Son
  • Publication number: 20180137677
    Abstract: A tile-based rendering method includes receiving a drawcall, determining a location of primitives in a frame based on the drawcall, dividing the frame into a plurality of tiles, and rendering the tiles, wherein the rendering includes determining a rendering order of the tiles based on primitives included in the tiles, and rendering the tiles according to the rendering order. A graphics processing unit (GPU) is configured to perform the tile-based rendering method, and may include a memory, a processor including at least one core and at least one cache. The GPU may execute a tile-based graphics pipeline for tile-based rendering of images, and allocate tiles including identical primitives to a core.
    Type: Application
    Filed: May 25, 2017
    Publication date: May 17, 2018
    Inventors: MIN-KYU JEONG, JAE-DON LEE, SANG-WON HA, MIN-YOUNG SON
  • Patent number: 9870042
    Abstract: A processing apparatus for managing power based on data is provided. The processing apparatus may obtain, in response to an access request from a processor for particular data stored in a memory, existing power information having a predefined correspondence to the particular data, and control a power mode of the processor based on the existing power information.
    Type: Grant
    Filed: May 12, 2014
    Date of Patent: January 16, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Min Young Son, Seung Won Lee, Shi Hwa Lee, Jae Don Lee, Chae Seok Im, Min Kyu Jeong
  • Publication number: 20170221255
    Abstract: An image processing method includes: determining whether a draw command that is identical to a previous draw command is input; obtaining information about a transparency of a previous frame that is performed with the previous draw command; and performing image processing on a current frame based on the information about the transparency.
    Type: Application
    Filed: April 11, 2017
    Publication date: August 3, 2017
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Min-kyu JEONG, Kwon-taek KWON, Min-young SON, Jeong-soo PARK, Sang-oak WOO
  • Publication number: 20170124723
    Abstract: A device for processing image data is disclosed. The device may determine a dominant texture with respect to each of a plurality of regions constituting an image. The device may group in a same group, from among the plurality of regions, regions in which the determined dominant texture is the same, and process allocated image data according to a result of grouping.
    Type: Application
    Filed: May 14, 2014
    Publication date: May 4, 2017
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jeong-soo PARK, Kwon-taek KWON, Jeong-ae PARK, Min-young SON, Min-kyu JEONG
  • Patent number: 9639971
    Abstract: An image processing method includes: determining whether a draw command that is identical to a previous draw command is input; obtaining information about a transparency of a previous frame that is performed with the previous draw command; and performing image processing on a current frame based on the information about the transparency.
    Type: Grant
    Filed: October 7, 2014
    Date of Patent: May 2, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min-kyu Jeong, Kwon-taek Kwon, Min-young Son, Jeong-soo Park, Sang-oak Woo