Abstract: Provided is a computing system having a hierarchical memory structure. When a data structure is allocated with respect to a task processed in the computing system, the data structure is divided and a portion of the data structure is allocated to a high speed memory of the hierarchical memory structure and a remaining data structure is allocated to a low speed memory of the hierarchical memory.

Abstract: Provided is a method and apparatus for preventing a stack overflow in an embedded system. The method of preventing a stack overflow includes: reading a maximum stack usage of at least one function for executing a requested operation from maximum stack usages of functions provided from a kernel, which are stored in advance; and processing the requested operation on the basis of the read maximum stack usage of the at least one function and a size of a usable region in a stack for the requested operation. Accordingly, the stack overflow can be prevented without generating a run-time overhead.

Abstract: An apparatus and method for dynamically reconfiguring an Operating System (OS) for a manycore system are provided. The apparatus may include an application type determining unit to determine a type of an executed application, and an OS reconfiguring unit to activate only at least one function in an OS, based on the determined type of the application, and to reconfigure the OS.

Abstract: Disclosed is a scratch pad memory management device and a method thereof. The scratch pad memory management device divides a scratch pad memory into a plurality of unit blocks, maintains a memory allocation table corresponding to indices of the plurality of unit blocks in a main memory, and manages the scratch pad memory.

Abstract: An apparatus for performing partition scheduling in a manycore environment. The apparatus may perform partition scheduling based on a priority and in this instance, may perform partition scheduling to minimize the number of idle cores. The apparatus may include a partition queue to manage a partition scheduling event; a partition scheduler including a core map to store hardware information of each of the plurality of cores; and a partition manager to perform partition scheduling with respect to the plurality of cores in response to the partition scheduling event, using the hardware information.

Abstract: Disclosed are a system, method and computer-readable medium related to processing debug information from an embedded system. Source code of an application program to be used in an embedded system may be compiled by a computing system. The application program may include a debug code line. A minimum amount of debug information is stored in an embedded system, reducing memory overhead and waste of clock cycles of a processor.

Abstract: Provided are graphics data rendering methods. The method includes obtaining, at a graphics data renderer, first space information of at least one object corresponding to graphics data of a first frame, determining a sampling mode of the first frame, based on the graphics data, and rendering graphics data of a second frame based on the first space information and the sampling mode of the first frame. Thus, memory space and time that are used for rendering graphics data may be reduced.

Abstract: Provided is a method of rendering an object. The method includes rendering extracting transparency information, at a object rendering apparatus, from a plurality of fragments, which comprise information representing at least one object in a frame, comparing depth information of at least one fragment, from among the plurality of fragments, located at a position of the frame, and determining a rendering of at least one fragment that is located in the position based on the comparison of the depth information and the transparency information.

Abstract: A scheduling method, medium and apparatus are provided. In the scheduling method, medium and apparatus, it is possible to prevent the possibility that the order between the priorities of the tasks represented by the expired timers and the tasks requested by the interrupt is reversed while also not deteriorating the performance of a real time operating system (RTOS), even though the number of timers expired when the interrupt occurs or that are already expired before the interrupt occurs is large, by selecting a timer for representing a point of time corresponding to a point of time when an interrupt occurs from among one or more timers each of which representing a task, a point of time assigned to the tasks, and a priority assigned to the task and executing a task represented by the selected timer and one or more tasks requested by the interrupt in order of priority.

Abstract: An image processing method includes: determining whether a draw command that is identical to a previous draw command is input; obtaining information about a transparency of a previous frame that is performed with the previous draw command; and performing image processing on a current frame based on the information about the transparency.

Abstract: An apparatus for electronic signature verification, including a grouping unit to group, into at least one group, a plurality of kernels included in an application to which electronic signature verification is to be performed, and an electronic signature verification unit to perform electronic signature verification with respect to the at least one group.

Abstract: A processing apparatus for managing power based on data is provided. The processing apparatus may obtain, in response to an access request from a processor for particular data stored in a memory, existing power information having a predefined correspondence to the particular data, and control a power mode of the processor based on the existing power information.

Abstract: A central processing unit (CPU) and a real-time scheduling method applicable in the CPU are disclosed. The CPU may determine a first task set and a second task set from among assigned tasks, schedule the determined first task set in a single core to enable the task to be processed, and schedule the determined second task set in a multi-core to enable the task to be processed.

Abstract: A synchronization scheduling apparatus and method in a real-time multi-core system are described. The synchronization scheduling apparatus may include a plurality of cores, each having at least one wait queue, a storage unit to store information regarding a first core receiving a wake-up signal in a previous cycle among the plurality of cores, and a scheduling processor to schedule tasks stored in the at least one wait queue, based on the information regarding the first core.

Abstract: Provided is a hardware acceleration apparatus, method and computer-readable medium efficiently processing multi-core synchronization. A processor core that fails to acquire a lock variable may be switched to a low power sleep mode and a waste of power may be reduced. Additionally, when a lock variable is returned, a wakeup signal may be transmitted to a processor core operated in the low power sleep mode, and the processor core may be activated.

Abstract: An apparatus and method for processing rendering data that may group vertex data that is received from a host computer, and may assign a shader processing unit to process a vertex shader among one or more shader processing units, and process the grouped vertex data using the assigned shader processing unit.

Abstract: An image processing apparatus. A rendering unit of the image processing apparatus may perform rendering with respect to each of N passes by applying a multi-pass rendering process with respect to an object in an image. The image processing apparatus may include a texture buffer to store information about at least one pixel using second pass rendering different from first pass rendering, while performing the first pass rendering corresponding to a process of generating a final result image among the N passes.

Abstract: An apparatus for electronic signature verification, including a grouping unit to group, into at least one group, a plurality of kernels included in an application to which electronic signature verification is to be performed, and an electronic signature verification unit to perform electronic signature verification with respect to the at least one group.

Abstract: A synchronization scheduling apparatus and method in a real-time multi-core system are described. The synchronization scheduling apparatus may include a plurality of cores, each having at least one wait queue, a storage unit to store information regarding a first core receiving a wake-up signal in a previous cycle among the plurality of cores, and a scheduling processor to schedule tasks stored in the at least one wait queue, based on the information regarding the first core.

Abstract: A method and apparatus transmitting and receiving in a real-time system are disclosed. The method of transmitting in a real-time system includes scheduling a task included in a socket based on a predetermined transmission option designated to the socket, and transmitting a packet generated by the scheduled task based on the predetermined transmission option, so that real-time communications of a network communication can be secured and resources of the system can be efficiently used, thereby, transmitting and receiving data according to the required characteristics of transmission and reception.