Abstract: A system with sound adjustment capability is provided. The system includes a head-mounted device, a first loudspeaker and a processor. The first loudspeaker is detachable from the head-mounted device. The processor is configured to detect a plurality of positions and a plurality of orientations of the head-mounted device and the first loudspeaker to determine whether the first loudspeaker is detached from the head-mounted device. The processor is further configured to modify a first audio signal by at least one first filter or at least one second filter to generate a filtered first audio signal. The at least one first filter is used when the first loudspeaker is coupled to the head-mounted device, and the at least one second filter is used when the first loudspeaker is detached from the head-mounted device. The filtered first audio signal is configured to drive the first loudspeaker.

Abstract: Embodiments of a 3D web interaction system are disclosed that allow a user to select a content item from a browser, displayed in an artificial reality environment, and present a corresponding version of the content item in the artificial reality environment. The 3D web interaction system can create the version of the selected content item in different ways depending on whether the selected content item is associated with 3D content and, if so, the type of the associated 3D content. For example, the 3D web interaction system can create and present different versions of the selected content item depending on whether the selected content item is(a) not associated with 3D content, (b) associated with “environment content,” or (c) associated with one or more 3D models.

Abstract: A server for knowledge recommendation for defect review. The server includes a processor electronically coupled to an electronic storage device storing a plurality of knowledge files related to wafer defects. The processor is configured to execute a set of instruction to cause the server to: receive a request for knowledge recommendation for inspecting an inspection image from a defect classification server; search for a knowledge file in the electronic storage device that matches the inspection image; and transmit the search result to the defect classification server.

Abstract: A model adjustment method, comprises: by a processing device, performing: obtaining inferred data that is inferred using a model, performing a feedback mechanism on the inferred data to obtain a feedback command associated with correctness of the inferred data, adjusting the inferred data according to the feedback command to generate adjusted data, and using the adjusted data as one of a plurality of pieces of training data for retraining the model. The present disclosure further provides a model adjustment system and non-transitory computer readable medium.

Abstract: Embodiments of a 3D web interaction system are disclosed that allow a user to select a content item from a browser, displayed in an artificial reality environment, and present a corresponding version of the content item in the artificial reality environment. The 3D web interaction system can create the version of the selected content item in different ways depending on whether the selected content item is associated with 3D content and, if so, the type of the associated 3D content. For example, the 3D web interaction system can create and present different versions of the selected content item depending on whether the selected content item is (a) not associated with 3D content, (b) associated with “environment content,” or (c) associated with one or more 3D models.

Abstract: Certain embodiments provide a method and non-transitory computer readable medium having instructions that, when executed by a processor of a processing system, cause the processing system to perform a method for improving operation of a semiconductor processing system. The method of part life estimation generally includes obtaining a chamber part having a first surface portion and second surface portion. A data matrix in the first portion of the chamber part is read. The data matrix has raised features. The first portion of the chamber part is cleaned. Wear on the raised features is evaluated. The part is discarded in response to the wear on the raised feature.

Abstract: A hafnium oxide-based ferroelectric field effect transistor includes a substrate, an isolation region arranged around the substrate; a gate structure including a buffer layer, a floating gate electrode, a hafnium oxide-based ferroelectric film layer, a control gate electrode and a film electrode layer which are sequentially stacked from bottom to top at a middle part of an upper surface of the substrate, a side wall arranged outside the gate structure, a source region and a drain region arranged oppositely at two sides of the gate structure and are formed by extending from an inner side of the isolation region to the middle part of the substrate, a first metal silicide layer formed by extending from the inner side of the isolation region to the side wall, and a second metal silicide layer arranged on an upper surface of the gate structure.

Abstract: Provided is a failure mode analysis method for a memory device including the following steps. A wafer is scanned by a test system to generate a failure pattern of the wafer, and a failure count of a single-bit in the wafer is obtained by a test program. A single-bit grouping table is defined according to a word-line layout, a bit-line layout, and an active area layout. A core group and a gap group are formed through grouping in at least one process in a self-aligned double patterning process. Failure counts of single-bits in the core group and the gap group are respectively counted to generate core failure data and gap failure data.

Abstract: Methods and apparatus for a baking chamber for processing a chamber component are provided herein. In some embodiments, a baking chamber includes: an enclosure defining a first chamber, wherein the first chamber comprises: a first chamber body having a first floor and first sidewalls that couple the first floor to a first lid of the first chamber body to define a first interior volume; a first support disposed in the first interior volume; a first gas line disposed in the first interior volume proximate the first lid; a first showerhead disposed between the first gas line and the first support; a first exhaust coupled to the first floor; and a first heater disposed in the first interior volume between the first support and the first floor; and wherein the enclosure includes a door configured to facilitate transferring the chamber component into and out of the enclosure.

Abstract: The invention provides a chip carrier, a chip testing module and a chip handling module. The chip carrier for carrying a plurality of chips comprises a main body with an upper surface and a lower surface. The main body has a plurality of air guide holes, and two ends of each air guide hole are respectively exposed on the upper surface and the lower surface. A part of the air guide holes are defined as a first group, and the air guide holes of the first group are connected. The main body is made of conductive material.

Abstract: A defect displaying method is provided in the disclosure. The method comprises acquiring defect group information from an image of a wafer, wherein the defect group information includes a set of correlations between a plurality of defects identified from the image and one or more corresponding assigned defect types and displaying at least some of the plurality of defects according to their corresponding assigned defect types.

Abstract: A sealing member is provided, including a plurality of nodes and a plurality of antinodes. Each sealing member can be rotated to expose nondamaged lobes for sealing, and prevents the sealing member from falling out of the lobed groove. A chamber is provided, including a groove that the sealing member is placed in. A method of rotating and placing the sealing member is provided, including a rotation to expose nondamaged portions of the sealing member.

Abstract: This invention discloses an inland river Lidar navigation system for vessels, comprising a receiver, a memory, a processor and a display. The processor coupled to the receiver and the memory, and the display coupled to the processor. Overall, the inland river navigation Lidar system based on Lidar is able to make use of the preset map data identification uncalculatable points of a point cloud of the predetermined procedure, thereby removing of the alignment step in traditional method can be omitted. Therefore, the processing speed can be improved.

Abstract: Provided is a failure mode analysis method for a memory device including the following steps. A wafer is scanned by a test system to generate a failure pattern of the wafer, and a failure count of a single-bit in the wafer is obtained by a test program. A single-bit grouping table is defined according to a word-line layout, a bit-line layout, and an active area layout. A core group and a gap group are formed through grouping in at least one process in a self-aligned double patterning process. Failure counts of single-bits in the core group and the gap group are respectively counted to generate core failure data and gap failure data.

Abstract: A method and an apparatus for controlling an air conditioner are provided, and the air conditioner is also provided. Herein, the method for controlling the air conditioner may include: acquiring at least one operating environment parameter of the air conditioner; determining a target temperature of the air conditioner and a revolving speed of an internal fan according to the at least one operating environment parameter of the air conditioner; and adjusting a frequency of a compressor on the basis of the operating environment parameter and the target temperature of the air conditioner and the revolving speed of the internal fan.

Abstract: A defect-detecting device stores a plurality of audio image data and a target audio image data. The plurality of audio image data include image data of normal audio and image data of defective audio of a first audio device and image data of normal audio of a second audio device, and the target audio image data corresponds to the second audio device. The defect-detecting device generates a plurality of simulated audio image data according to the plurality of audio image data, and trains a defect detection model according to the simulated audio image data. The defect-detecting device also analyzes, through the defect detection model, the target audio image data, so as to determine whether the second audio device is defective.

Abstract: A NAND ferroelectric memory cell with a three-dimensional structure and a preparation method thereof are provided, the ferroelectric memory cell comprises: an oxide insulating layer, a channel layer, a channel buffer layer, a ferroelectric layer, and/or a gate buffer layer, and a gate arranged successively from the inside to the outside. In the memory cell of the present disclosure, the buffer layer has the following effects: 1. It can induce the crystallization of ferroelectric film to form ferroelectric phase; 2. It can reduce adverse effects caused by different crystalline characteristics of the channel layer and the ferroelectric layer, improve the quality and uniformity of the deposited film; 3. It can enhance the interface property of the channel layer, reduce leakage current, and enhance endurance of the device. Therefore, the buffer layer can improve the overall storage property and homogeneity of memory cells with a three-dimensional structure.

Abstract: A SRAM structure includes a first SRAM cell, a second SRAM cell arranged in mirror symmetry with the first SRAM cell along a first direction, a third SRAM cell arranged in mirror symmetry with the first SRAM cell along a second direction perpendicular to the first direction, and a fourth SRAM cell arranged in mirror symmetry with the third SRAM cell along the first direction and arranged in mirror symmetry with the second SRAM cell along the second direction. Each of SRAM cells includes a first and a second pull-down transistor. The SRAM structure further includes a contact bar extending in the second direction to sources of the second pull-down transistors of the first and third SRAM cells and extending in a third direction opposite to the second direction to sources of the second pull-down transistors of the second and fourth SRAM cells.

Abstract: A hafnium oxide-based ferroelectric field effect transistor includes a substrate, an isolation region arranged around the substrate; a gate structure including a buffer layer, a floating gate electrode, a hafnium oxide-based ferroelectric film layer, a control gate electrode and a film electrode layer which are sequentially stacked from bottom to top at a middle part of an upper surface of the substrate, a side wall arranged outside the gate structure, a source region and a drain region arranged oppositely at two sides of the gate structure and are formed by extending from an inner side of the isolation region to the middle part of the substrate, a first metal silicide layer formed by extending from the inner side of the isolation region to the side wall, and a second metal silicide layer arranged on an upper surface of the gate structure.

Abstract: A gate-last ferroelectric field effect transistor includes a substrate, isolation regions, a gate structure, a side wall spacer, source and drain regions, a first metal silicide layer and an interlayer dielectric layer which are sequentially arranged from bottom to top; the present disclosure further provides a manufacturing method of a gate-last ferroelectric field effect transistor; according to structural characteristics of the gate-last ferroelectric field effect transistor and crystalline characteristics of a hafnium oxide-based ferroelectric film, a dummy gate is first introduced in a manufacturing process of the gate-last ferroelectric field effect transistor; afterwards, high-temperature annealing is performed to make sure that an unannealed hafnium oxide-based film is crystallized to form a ferroelectric phase; finally the dummy gate is removed and a gate electrode layer is deposited to meet performance requirements of the gate-last ferroelectric field effect transistor; and the gate-last ferroelectr