Abstract: The invention provides a chip carrier, a chip testing module and a chip handling module. The chip carrier for carrying a plurality of chips comprises a main body with an upper surface and a lower surface. The main body has a plurality of air guide holes, and two ends of each air guide hole are respectively exposed on the upper surface and the lower surface. A part of the air guide holes are defined as a first group, and the air guide holes of the first group are connected. The main body is made of conductive material.

Abstract: Methods and apparatus for a baking chamber for processing a chamber component are provided herein. In some embodiments, a baking chamber includes: an enclosure defining a first chamber, wherein the first chamber comprises: a first chamber body having a first floor and first sidewalls that couple the first floor to a first lid of the first chamber body to define a first interior volume; a first support disposed in the first interior volume; a first gas line disposed in the first interior volume proximate the first lid; a first showerhead disposed between the first gas line and the first support; a first exhaust coupled to the first floor; and a first heater disposed in the first interior volume between the first support and the first floor; and wherein the enclosure includes a door configured to facilitate transferring the chamber component into and out of the enclosure.

Abstract: A defect displaying method is provided in the disclosure. The method comprises acquiring defect group information from an image of a wafer, wherein the defect group information includes a set of correlations between a plurality of defects identified from the image and one or more corresponding assigned defect types and displaying at least some of the plurality of defects according to their corresponding assigned defect types.

Abstract: A sealing member is provided, including a plurality of nodes and a plurality of antinodes. Each sealing member can be rotated to expose nondamaged lobes for sealing, and prevents the sealing member from falling out of the lobed groove. A chamber is provided, including a groove that the sealing member is placed in. A method of rotating and placing the sealing member is provided, including a rotation to expose nondamaged portions of the sealing member.

Abstract: Provided is a failure mode analysis method for a memory device including the following steps. A wafer is scanned by a test system to generate a failure pattern of the wafer, and a failure count of a single-bit in the wafer is obtained by a test program. A single-bit grouping table is defined according to a word-line layout, a bit-line layout, and an active area layout. A core group and a gap group are formed through grouping in at least one process in a self-aligned double patterning process. Failure counts of single-bits in the core group and the gap group are respectively counted to generate core failure data and gap failure data.

Abstract: This invention discloses an inland river Lidar navigation system for vessels, comprising a receiver, a memory, a processor and a display. The processor coupled to the receiver and the memory, and the display coupled to the processor. Overall, the inland river navigation Lidar system based on Lidar is able to make use of the preset map data identification uncalculatable points of a point cloud of the predetermined procedure, thereby removing of the alignment step in traditional method can be omitted. Therefore, the processing speed can be improved.

Abstract: A method and an apparatus for controlling an air conditioner are provided, and the air conditioner is also provided. Herein, the method for controlling the air conditioner may include: acquiring at least one operating environment parameter of the air conditioner; determining a target temperature of the air conditioner and a revolving speed of an internal fan according to the at least one operating environment parameter of the air conditioner; and adjusting a frequency of a compressor on the basis of the operating environment parameter and the target temperature of the air conditioner and the revolving speed of the internal fan.

Abstract: A defect-detecting device stores a plurality of audio image data and a target audio image data. The plurality of audio image data include image data of normal audio and image data of defective audio of a first audio device and image data of normal audio of a second audio device, and the target audio image data corresponds to the second audio device. The defect-detecting device generates a plurality of simulated audio image data according to the plurality of audio image data, and trains a defect detection model according to the simulated audio image data. The defect-detecting device also analyzes, through the defect detection model, the target audio image data, so as to determine whether the second audio device is defective.

Abstract: A NAND ferroelectric memory cell with a three-dimensional structure and a preparation method thereof are provided, the ferroelectric memory cell comprises: an oxide insulating layer, a channel layer, a channel buffer layer, a ferroelectric layer, and/or a gate buffer layer, and a gate arranged successively from the inside to the outside. In the memory cell of the present disclosure, the buffer layer has the following effects: 1. It can induce the crystallization of ferroelectric film to form ferroelectric phase; 2. It can reduce adverse effects caused by different crystalline characteristics of the channel layer and the ferroelectric layer, improve the quality and uniformity of the deposited film; 3. It can enhance the interface property of the channel layer, reduce leakage current, and enhance endurance of the device. Therefore, the buffer layer can improve the overall storage property and homogeneity of memory cells with a three-dimensional structure.

Abstract: A SRAM structure includes a first SRAM cell, a second SRAM cell arranged in mirror symmetry with the first SRAM cell along a first direction, a third SRAM cell arranged in mirror symmetry with the first SRAM cell along a second direction perpendicular to the first direction, and a fourth SRAM cell arranged in mirror symmetry with the third SRAM cell along the first direction and arranged in mirror symmetry with the second SRAM cell along the second direction. Each of SRAM cells includes a first and a second pull-down transistor. The SRAM structure further includes a contact bar extending in the second direction to sources of the second pull-down transistors of the first and third SRAM cells and extending in a third direction opposite to the second direction to sources of the second pull-down transistors of the second and fourth SRAM cells.

Abstract: Certain embodiments provide a method and non-transitory computer readable medium comprising instructions that, when executed by a processor of a processing system, cause the processing system to perform a method for improving operation of a semiconductor processing system. The method of part life estimation generally includes obtaining a chamber part having a first surface portion and second surface portion. A data matrix in the first portion of the chamber part is read. The data matrix has raised features. The first portion of the chamber part is cleaned. Wear on the raised features is evaluated. The part is discarded in response to the wear on the raised feature.

Abstract: A gate-last ferroelectric field effect transistor includes a substrate, isolation regions, a gate structure, a side wall spacer, source and drain regions, a first metal silicide layer and an interlayer dielectric layer which are sequentially arranged from bottom to top; the present disclosure further provides a manufacturing method of a gate-last ferroelectric field effect transistor; according to structural characteristics of the gate-last ferroelectric field effect transistor and crystalline characteristics of a hafnium oxide-based ferroelectric film, a dummy gate is first introduced in a manufacturing process of the gate-last ferroelectric field effect transistor; afterwards, high-temperature annealing is performed to make sure that an unannealed hafnium oxide-based film is crystallized to form a ferroelectric phase; finally the dummy gate is removed and a gate electrode layer is deposited to meet performance requirements of the gate-last ferroelectric field effect transistor; and the gate-last ferroelectr

Abstract: A hafnium oxide-based ferroelectric field effect transistor includes a substrate, an isolation region arranged around the substrate; a gate structure including a buffer layer, a floating gate electrode, a hafnium oxide-based ferroelectric film layer, a control gate electrode and a film electrode layer which are sequentially stacked from bottom to top at a middle part of an upper surface of the substrate, a side wall arranged outside the gate structure, a source region and a drain region arranged oppositely at two sides of the gate structure and are formed by extending from an inner side of the isolation region to the middle part of the substrate, a first metal silicide layer formed by extending from the inner side of the isolation region to the side wall, and a second metal silicide layer arranged on an upper surface of the gate structure.

Abstract: A method for cleaning a semiconductor substrate is provided. The method includes the steps of: applying a first agent onto a top surface of the semiconductor substrate while the semiconductor substrate is rotated at a first rotational frequency; immersing the semiconductor substrate in a second agent while rotating the semiconductor substrate at a second rotational frequency; and rotating the semiconductor substrate at a third rotational frequency while a third agent is introduced onto the top surface of the semiconductor substrate. The first rotational frequency may be greater than the third rotational frequency and the third rotational frequency is greater than the second rotational frequency. In some embodiments, the second rotational frequency is zero and the semiconductor substrate is held stationary during the immersing step.

Abstract: The present invention discloses a vessel collision avoiding system and method based on Artificial Potential Field algorithm, the method comprises the following steps: (S1) obtaining a vessel information, at least one obstacle information and a target information; (S2) establishing an Artificial Potential Field (APF) by the vessel information, the at least one obstacle information and the target information, wherein the Artificial Potential Field comprises an attractive field of the target and a repulsive field of the obstacle; (S3) combining the attractive field and the repulsive field to obtain a first resultant force; (S4) Adding an external force to the Artificial Potential Field based on the vessel information or the obstacle information; (S5) combining the first resultant force and the external force to obtain a second resultant force; and (S6) the vessel sails in the direction of the second resultant force to avoid the obstacle.

Abstract: The present disclosure relates to systems and methods for semiconductor tool part tracking and kit verification. Data relating to part identification and performance are encoded to a unique code that is encoded into machine-readable form, such as a data matrix. A multi-dimensional array (MDA) of the data matrices of a group of parts is a ‘golden MDA’. When assembled into a kit, the parts are scanned and compared to the golden MDA. If there's a match, a kit unique code is used to generate a kit data matrix. The part data matrix codes are provided to a database to determine if a part combination will cause a coupling effect, based on part usage history.

Abstract: The present invention discloses an autonomous vessel simulation system, comprising an environment model building system, a vessel model building system and a central processing system. The environment model building system builds at least one environment model; the vessel model building system builds at least one vessel model and an operation module of the central processing system integrates the environment model and the vessel model. The vessel model is navigated in the environment model according to at least one navigational parameter, and a display module displays the navigation status of the vessel model. In addition, an operating method of the autonomous vessel simulation system is also provided.

Abstract: The present disclosure is directed to a system and method to identify and track parts of a semiconductor processing chamber, as well as the status of the parts, and store status information in a centralized location as status changes over time.

Abstract: A sound reproducing method used in sound reproducing apparatus that includes the steps outlined below is provided. An input sound signal related to listener data and sound source data is received. An encoding process is performed by multiplying the input sound signal by an encoding function matrix having entries related to a basis function to generate an encoding result. A decoding function matrix is retrieved from the storage and at least one direction parameter is applied to the decoding function matrix, wherein the decoding function matrix compensates a difference between an ideal approximation result and a modeled approximation result of the input sound signal. A decoding process is performed by multiplying the encoding result by the decoding function matrix having the direction parameter applied to generate an output sound signal. The output sound signal is reproduced.

Abstract: A network security system and method thereof are provided in this disclosure. The network security system includes a server and a client device. The client device is configured for running a firewall according to a first parameter corresponding to at least one setting category, and receiving a second parameters transmitted by the server within a periodic communication interval. The client device further includes a monitoring unit. The monitoring unit is configured for checking automatically whether a setting category of the second parameter matches the at least one setting category during a communication period between the server and the client device; if the setting category of the second parameter matches the at least one setting category, setting up the firewall according to the second parameter; and if the second parameter corresponding to setting category does not match the at least one setting category, omitting the second parameter.