Patents by Inventor Min Peng

Min Peng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250050272
    Abstract: The present invention provides a gas processing module, a gas processing method and a gas-phase organic compound processing method. A gas processing module comprises a cavity, a gas input unit, a light source, a photocatalyst, a liquid input unit, a gas discharge unit and a liquid discharge unit. The gas input unit is communicated with the inside of the cavity and used for supplying a to-be-processed gas comprising a gas-phase organic compound into the cavity. The light source is arranged in the cavity and used for providing a first light. The photocatalyst is arranged in the cavity, and at least a portion of the gas-phase organic compound of the to-be-processed gas which comes into contact with the photocatalyst generates an organic compound product under the action of the photocatalyst when irradiated by the first light.
    Type: Application
    Filed: August 9, 2024
    Publication date: February 13, 2025
    Applicant: GREENFILTEC LTD.
    Inventors: Yi-Hui YU, Kuo-Min PENG, Yu-De LIEN, Ju-Ting LEE
  • Publication number: 20250017895
    Abstract: This disclosure is directed to methods of treating or inhibiting mitochondrial dysfunction or mitochondrial disease in a subject comprising administration of and effective amount of one or more of (+) Epicatechin (?) epicatechin, 11-hydroxyprogesterone, and 11-?-hydroxypregnenolone and other efficacious agents in a pharmaceutically acceptable carrier. Agents can be administered alone or in certain synergistic combinations. The compositions and methods described effectively reduce or alleviate primary respiratory chain dysfunction symptoms, and have efficacy for improving cellular resiliency, stress resistance, and symptoms associated with primary, secondary, or acute respiratory chain dysfunction.
    Type: Application
    Filed: November 29, 2022
    Publication date: January 16, 2025
    Applicant: THE CHILDREN'S HOSPITAL OF PHILADELPHIA
    Inventors: Marni J. FALK, Neal D. MATHEW, Eiko NAKAMARU-OGISO REINGEWIRTZ, Min PENG, Erzsebet POLYAK, Bhumi SHAH
  • Patent number: 12062151
    Abstract: An image processing circuit performs super-resolution (SR) operations. The image processing circuit includes memory to store multiple parameter sets of multiple artificial intelligence (AI) models. The image processing circuit further includes an image guidance module, a parameter decision module, and an SR engine. The image guidance module operates to detect a representative feature in an image sequence including a current frame and past frames within a time window. The parameter decision module operates to adjust parameters of one or more AI models based on a measurement of the representative feature. The SR engine operates to process the current frame using the one or more AI models with the adjusted parameters to thereby generate a high-resolution image for display.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: August 13, 2024
    Assignee: MediaTek Inc.
    Inventors: Ming-En Shih, Ping-Yuan Tsai, Yu-Cheng Tseng, Kuo-Chen Huang, Kuo-Chiang Lo, Hsin-Min Peng, Chun Hsien Wu, Pei-Kuei Tsung, Tung-Chien Chen, Yao-Sheng Wang, Cheng Lung Jen, Chih-Wei Chen, Chih-Wen Goo, Yu-Sheng Lin, Tsu Jui Hsu
  • Patent number: 12013759
    Abstract: A method includes receiving, by an electronic device, an instruction for wiping data or performing a factory reset, setting an identifier according to the instruction, shutting down or restarting electronic device, reading the identifier when the electronic device is powered on or is connected to a network, sending a request to a server to request the server to delete a security service from a secure element (SE), receiving a command from the server, where the command instructs the electronic device to delete a target security service from the SE, and the target security service is based on a security service installed in the SE and a list of deletable security services stored in the server, and deleting, a secure element applet corresponding to the target security service from the SE according to the first command.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: June 18, 2024
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Zhuofei Li, Min Peng, Gaosheng Yin
  • Publication number: 20240129619
    Abstract: A method includes detecting a trigger operation of a user on a control on a first interface of the terminal device, where the control is used to obtain target data; and in response to the trigger operation of the user, performing a first action and a second action that correspond to the control, where the first action is used to open and display a second interface, and the second action is used to obtain, through matching, information that is on the second interface and that is related to the target data.
    Type: Application
    Filed: January 21, 2022
    Publication date: April 18, 2024
    Inventor: Min Peng
  • Patent number: 11755211
    Abstract: A data storage device including, in one implementation, a NAND memory and a controller. The NAND memory includes a read/write circuit configured to determine and store initial physical column addresses for each plane included in the NAND memory. The controller is configured to send a read-transfer command and a one-byte address to the NAND memory. The read/write circuit is also configured to retrieve a first initial physical column address from the initial physical column addresses stored in the NAND memory after the NAND memory receives the one-byte address from the controller. The first initial physical column address is associated with a die address and a plane address included in the one-byte address. The read/write circuit is further configured to retrieve a first set of data stored at the first initial physical column address. The read/write circuit is also configured to output the first set of data to the controller.
    Type: Grant
    Filed: October 3, 2022
    Date of Patent: September 12, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Grishma Shah, Daniel Tuers, Sahil Sharma, Hua-Ling Cynthia Hsu, Yenlung Li, Min Peng
  • Publication number: 20230022998
    Abstract: A data storage device including, in one implementation, a NAND memory and a controller. The NAND memory includes a read/write circuit configured to determine and store initial physical column addresses for each plane included in the NAND memory. The controller is configured to send a read-transfer command and a one-byte address to the NAND memory. The read/write circuit is also configured to retrieve a first initial physical column address from the initial physical column addresses stored in the NAND memory after the NAND memory receives the one-byte address from the controller. The first initial physical column address is associated with a die address and a plane address included in the one-byte address. The read/write circuit is further configured to retrieve a first set of data stored at the first initial physical column address. The read/write circuit is also configured to output the first set of data to the controller.
    Type: Application
    Filed: October 3, 2022
    Publication date: January 26, 2023
    Inventors: Grishma Shah, Daniel Tuers, Sahil Sharma, Hua-Ling Cynthia Hsu, Yenlung Li, Min Peng
  • Patent number: 11521327
    Abstract: Disclosed is a detection target positioning method and device. The method comprises: acquiring an original image and pre-processing the original image to obtain a gradation of each pixel in a target gradation image corresponding to a target region including a detection target; calculating first gradation sets corresponding to rows of pixels of the target gradation image and second gradation sets corresponding to columns of pixels of the target gradation image; and determining rows of two ends of the detection target in a column direction according to the first gradation sets, determining columns of two ends of the detection target in a row direction according to the second gradation sets, and determining a center of the detection target according to the row of two ends of the detection target in the column direction and the columns of two ends of the detection target in the row direction.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: December 6, 2022
    Assignee: BEIJING BOE TECHNOLOGY DEVELOPMENT CO., LTD.
    Inventors: Fuyin Wang, Ruoyu Huang, Min Peng, Yue Li
  • Patent number: 11487446
    Abstract: A data storage device including, in one implementation, a NAND memory and a controller. The NAND memory includes a read/write circuit configured to determine and store initial physical column addresses for each plane included in the NAND memory. The controller is configured to send a read-transfer command and a one-byte address to the NAND memory. The read/write circuit is also configured to retrieve a first initial physical column address from the initial physical column addresses stored in the NAND memory after the NAND memory receives the one-byte address from the controller. The first initial physical column address is associated with a die address and a plane address included in the one-byte address. The read/write circuit is further configured to retrieve a first set of data stored at the first initial physical column address. The read/write circuit is also configured to output the first set of data to the controller.
    Type: Grant
    Filed: February 12, 2021
    Date of Patent: November 1, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Grishma Shah, Daniel Tuers, Sahil Sharma, Hua-Ling Cynthia Hsu, Yenlung Li, Min Peng
  • Patent number: 11386961
    Abstract: In a non-volatile memory circuit, performance is improved by converting data between a serial format, for transfer on and off of the memory circuit, and a parallel format, for transfer to and from the memory latches used for read and writing data into the memory array of the memory circuit. The memory array is split into M+N divisions, but transferred with a degree of parallelism of M, allowing M words of data to be transferred in parallel at a fixed transfer rate while allowing for up to N bad columns in a transfer. In the write path, a column skipping mechanism is used when converting words of write data into a parallel format. In the read path, a set of (M+N) to 1 multiplexers is used to align the word of read data so that read data can be transferred at a fixed rate and without any added latency.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: July 12, 2022
    Assignee: SanDisk Technologies LLC
    Inventors: YenLung Li, Chen Chen, Min Peng, Mitsuyuki Watanabe
  • Patent number: 11380417
    Abstract: Aspects of a storage device are provided that reduce calculations for identifying physical locations of data during a read operation. In one aspect, a memory device includes one or more memory arrays. Each array includes multiple chunks of memory. The device includes a first set of registers for storing prefixed starting addresses for each array. The device further includes control logic that may identify bad physical address in each array. For each successive chunk in each array and based on the prefixed starting address and the bad physical address locations, the device may determine a pointer to a starting physical address for the chunk. The pointer may be stored in a second set of registers for use in register read operations.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: July 5, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Cynthia Hsu, YenLung Li, Min Peng
  • Publication number: 20220179568
    Abstract: A data storage device including, in one implementation, a NAND memory and a controller. The NAND memory includes a read/write circuit configured to determine and store initial physical column addresses for each plane included in the NAND memory. The controller is configured to send a read-transfer command and a one-byte address to the NAND memory. The read/write circuit is also configured to retrieve a first initial physical column address from the initial physical column addresses stored in the NAND memory after the NAND memory receives the one-byte address from the controller. The first initial physical column address is associated with a die address and a plane address included in the one-byte address. The read/write circuit is further configured to retrieve a first set of data stored at the first initial physical column address. The read/write circuit is also configured to output the first set of data to the controller.
    Type: Application
    Filed: February 12, 2021
    Publication date: June 9, 2022
    Inventors: Grishma Shah, Daniel Tuers, Sahil Sharma, Hua-Ling Cynthia Hsu, Yenlung Li, Min Peng
  • Publication number: 20210397518
    Abstract: A method includes receiving, by an electronic device, an instruction for wiping data or performing a factory reset, setting an identifier according to the instruction, shutting down or restarting electronic device, reading the identifier when the electronic device is powered on or is connected to a network, sending a request to a server to request the server to delete a security service from a secure element (SE), receiving a command from the server, where the command instructs the electronic device to delete a target security service from the SE, and the target security service is based on a security service installed in the SE and a list of deletable security services stored in the server, and deleting, a secure element applet corresponding to the target security service from the SE according to the first command.
    Type: Application
    Filed: November 13, 2019
    Publication date: December 23, 2021
    Inventors: Zhuofei Li, Min Peng, Gaosheng Yin
  • Publication number: 20210358823
    Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a semiconductor package structure includes a semiconductor die and a light absorbing layer. The semiconductor die has a first surface, a second surface and a third surface. An active layer of the semiconductor die is adjacent to the first surface. The second surface is opposite to the first surface. The third surface extends from the first surface to the second surface. The light absorbing layer covers the second surface and the third surface of the semiconductor die. The semiconductor die has a thickness defined from the first surface to the second surface, and the thickness of the semiconductor die is less than or equal to about 300 micrometers (?m).
    Type: Application
    Filed: May 18, 2020
    Publication date: November 18, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chi Sheng TSENG, Lu-Ming LAI, Yu-Che HUANG, Shih-Chieh TANG, Yu-Min PENG, Hui-Chung LIU
  • Publication number: 20210338615
    Abstract: Provided are methods for treating or preventing T cell-mediated diseases or disorders by administering an inhibitor of acetyl-CoA production, such as an inhibitor of lactate dehydrogenase A or an inhibitor of ATP-citrate lyase.
    Type: Application
    Filed: July 9, 2021
    Publication date: November 4, 2021
    Inventors: Ming Li, Min Peng, Na Yin
  • Publication number: 20210287338
    Abstract: An image processing circuit performs super-resolution (SR) operations. The image processing circuit includes memory to store multiple parameter sets of multiple artificial intelligent (AI) models. The image processing circuit further includes an image guidance module, a parameter decision module, and an SR engine. The image guidance module operates to detect a representative feature in an image sequence including a current frame and past frames within a time window. The parameter decision module operates to adjust parameters of one or more AI models based on a measurement of the representative feature. The SR engine operates to process the current frame using the one or more AI models with the adjusted parameters to thereby generate a high-resolution image for display.
    Type: Application
    Filed: December 10, 2020
    Publication date: September 16, 2021
    Inventors: Ming-En Shih, Ping-Yuan Tsai, Yu-Cheng Tseng, Kuo-Chen Huang, Kuo-Chiang Lo, Hsin-Min Peng, Chun Hsien Wu, Pei-Kuei Tsung, Tung-Chien Chen, Yao-Sheng Wang, Cheng Lung Jen, Chih-Wei Chen, Chih-Wen Goo, Yu-Sheng Lin, Tsu Jui Hsu
  • Patent number: D974373
    Type: Grant
    Filed: October 13, 2020
    Date of Patent: January 3, 2023
    Assignee: Meta Platforms, Inc.
    Inventors: Isaac Rose, Min Peng, Courtney Neal, Ron Besseling
  • Patent number: D1015314
    Type: Grant
    Filed: April 16, 2022
    Date of Patent: February 20, 2024
    Inventor: Min Peng
  • Patent number: D1015315
    Type: Grant
    Filed: April 16, 2022
    Date of Patent: February 20, 2024
    Inventor: Min Peng
  • Patent number: D1023999
    Type: Grant
    Filed: April 16, 2022
    Date of Patent: April 23, 2024
    Inventor: Min Peng