Patents by Inventor Min Peng

Min Peng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210287339
    Abstract: An image processing apparatus includes a super-resolution (SR) circuit and a resizer circuit. The SR circuit performs an SR operation upon a first image to generate a second image, wherein a resolution of the second image is not lower than a resolution of the first image, and the SR operation is based, at least in part, on one or more artificial intelligence (AI) models. The resizer circuit performs a resize operation upon the second image to generate a third image, wherein a resolution of the third image is not lower than the resolution of the second image, and no AI model is involved in the resize operation.
    Type: Application
    Filed: March 9, 2021
    Publication date: September 16, 2021
    Inventors: Ming-En Shih, Yu-Cheng Tseng, Kuo-Chen Huang, Pei-Kuei Tsung, Hsin-Min Peng, Ping-Yuan Tsai, Kuo-Chiang Lo, Chun-Hsien Wu, Chih-Wei Chen, Cheng-Lung Jen
  • Publication number: 20210193226
    Abstract: In a non-volatile memory circuit, performance is improved by converting data between a serial format, for transfer on and off of the memory circuit, and a parallel format, for transfer to and from the memory latches used for read and writing data into the memory array of the memory circuit. The memory array is split into M+N divisions, but transferred with a degree of parallelism of M, allowing M words of data to be transferred in parallel at a fixed transfer rate while allowing for up to N bad columns in a transfer. In the write path, a column skipping mechanism is used when converting words of write data into a parallel format. In the read path, a set of (M+N) to 1 multiplexers is used to align the word of read data so that read data can be transferred at a fixed rate and without any added latency.
    Type: Application
    Filed: December 20, 2019
    Publication date: June 24, 2021
    Applicant: SanDisk Technologies LLC
    Inventors: YenLung Li, Chen Chen, Min Peng, Mitsuyuki Watanabe
  • Patent number: 10971202
    Abstract: Apparatuses and techniques are described for transferring data out of a memory device with low latency. Data can be stored in data transfer latches for NAND strings arranged in columns in divisions of a block. Data can be output from the data transfer latches for different columns in different divisions in each transfer. For example, the data output can include data from an nth column in some divisions and an n+1st column in other divisions. This avoids outputting unwanted data at the start of a data transfer. The data from the data transfer latches is output to a data pipeline and then to a set of control latch circuits. The data can be clocked out from a last control latch circuit of the set in a desired division order by use of separate multiplexer control signals for the control latch circuits.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: April 6, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Chen Chen, Yenlung Li, Min Peng
  • Patent number: 10838726
    Abstract: Apparatuses and techniques are described for accessing redundant columns of data in a memory device. To facilitate scaling of a memory device and reduce a clock rate used to access latches of the redundant columns in program and read operations, one or more first-in, first out (FIFO) buffers are provided to output data to, and receive data from, the latches. The FIFO buffers act as an interface between a controller and the latches, and exchange data with the controller at a relatively high clock rate, and exchange data with the latches of the redundant columns at a slower clock rate. During a read operation, the FIFO can prefetch read data from one or more columns and store it until it is needed to replace the data of a defective primary column.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: November 17, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Min Peng, Yenlung Li, Chen Chen
  • Patent number: 10825526
    Abstract: In non-volatile memory circuit, the area devoted to the cache buffer of the read and write circuitry is reduced through the sharing of data latches. In an array structure where memory cells are connected along bit lines, and the bit lines organized into columns, each of the columns has an associated set of data latches, including one or more data latches for each bit line of the column. Data is transferred in and out of the read and write circuit on a data bus, where data is transferred between the data latches and the data bus through a set of transfers latches. The area used by the latch structure is reduced by sharing the transfer latches of the read and write circuitry between the data latches of multiple columns.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: November 3, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: YenLung Li, Hua-Ling Cynthia Hsu, Chen Chen, Min Peng
  • Patent number: 10811082
    Abstract: In a non-volatile memory circuit, read and write performance is improved by increasing the transfer rate of data through the cache buffer during read and write operations. In an array structure where memory cells are connected along bit lines, and the bit lines organized into columns, pairs of data words are stored interleaved on the bit lines of a pair of columns. Data is transferred in and out of the read and write circuit on an internal bus structure, where part of the transfer of one word stored on a pair of columns can overlap with part of the transfer of another word, accelerating transfer times for both read and write.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: October 20, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: YenLung Li, Hua-Ling Cynthia Hsu, Chen Chen, Min Peng
  • Patent number: 10790323
    Abstract: A semiconductor device package includes a semiconductor device, an optical conductive pillar, a first encapsulant and a second encapsulant. The semiconductor device includes a pixel. The optical conductive pillar is disposed on the pixel. The first encapsulant has a first thickness and encapsulates the optical conductive pillar. The second encapsulant has a second thickness different from the first thickness.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: September 29, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Yu-Min Peng
  • Patent number: 10782184
    Abstract: The present disclosure relates to an optical device. The optical device comprises an electronic component, a plurality of light conducting pillars and an opaque layer. The electronic component includes a plurality of pixels. Each of the light conducting pillars is disposed over a corresponding pixel of the plurality of pixels of the electronic component. The opaque layer covers a lateral surface of each of the light conducting pillars.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: September 22, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yu-Min Peng, Ching-Han Huang, Lu-Ming Lai
  • Patent number: 10726940
    Abstract: Apparatuses, systems, and methods are disclosed for skip inconsistency correction. A skip circuit is configured to skip memory units for read operations and write operations of a memory array, based on a record of memory units identified as faulty. A skip inconsistency detection circuit is configured to detect a skip inconsistency in read data from a memory array. A correction circuit is configured to correct a skip inconsistency and output corrected read data.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: July 28, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Zhuojie Li, Hua-Ling Cynthia Hsu, Yen-Lung Li, Min Peng
  • Patent number: 10712585
    Abstract: Embodiments of the present disclosure provide an optical grating and a 3D display device having the same. The optical grating comprises a plurality of grating units arranged from a center of the optical grating towards two sides thereof, values of grating periods of a plurality of said grating units on either side of the center being non-linearly decreased progressively from the center to the side.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: July 14, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Guobing Yin, Jiyang Shao, Min Peng, Xingdong Liu, Yuting Zhang
  • Patent number: 10664110
    Abstract: The present disclosure relates to a touch panel controller, a control information acquisition method and a touch display device in the field of display technology. The touch panel controller includes at least two conductive members and a rotating component. The rotating component includes a supporting component and a mounting component connected to each other. The mounting component is configured to have the at least two conductive members mounted thereon. One end of the supporting component is configured to determine a placement surface that is in contact with a touch panel. A distance between each of the at least two conductive members and the placement surface is less than a sensing distance, and the sensing distance is a distance at which a capacitance change caused by the conductive member is detectable by the touch panel.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: May 26, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Guobing Yin, Min Peng, Jiyang Shao, Xingdong Liu, Yuting Zhang
  • Publication number: 20200082897
    Abstract: Apparatuses, systems, and methods are disclosed for skip inconsistency correction. A skip circuit is configured to skip memory units for read operations and write operations of a memory array, based on a record of memory units identified as faulty. A skip inconsistency detection circuit is configured to detect a skip inconsistency in read data from a memory array. A correction circuit is configured to correct a skip inconsistency and output corrected read data.
    Type: Application
    Filed: January 3, 2019
    Publication date: March 12, 2020
    Applicant: SanDisk Technologies LLC
    Inventors: ZHUOJIE LI, HUA-LING CYNTHIA HSU, YEN-LUNG LI, MIN PENG
  • Patent number: 10564438
    Abstract: A slit grating and a three-dimensional (3D) display apparatus including the slit grating are disclosed herein, the slit grating includes a plurality of grating structures (11-17) arranged side by side. The widths of the grating structures (11-17) increase and then decrease, along the direction in which the grating structures (11-17) are arranged. A grating structure (13,14) having the largest width may define a trend change point after which the trend in the widths of the grating structure widths changes.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: February 18, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xingdong Liu, Guobing Yin, Min Peng, Jiyang Shao, Ke Chao, Yuting Zhang
  • Publication number: 20190321314
    Abstract: Provided are methods for treating or preventing T cell-mediated diseases or disorders by administering an inhibitor of acetyl-CoA production, such as an inhibitor of lactate dehydrogenase A or an inhibitor of ATP-citrate lyase.
    Type: Application
    Filed: September 15, 2017
    Publication date: October 24, 2019
    Inventors: Ming Li, Min Peng, Na Yin
  • Patent number: 10416364
    Abstract: A curved grating structure, a display panel and the display device are provided. The curved grating structure includes multiple grating strips spaced from each other. Grating intervals between adjacent grating strips are successively decreased from a center point of the curved grating structure to a terminal of the curved grating structure. The grating interval between two adjacent grating strips is a distance in a first direction between center points of the two adjacent grating strips, and the first direction is a direction perpendicular to a normal vector of the curved grating structure passing through a center point of the curved grating structure.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: September 17, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yuting Zhang, Ke Chao, Guobing Yin, Jiyang Shao, Min Peng, Xingdong Liu
  • Publication number: 20190267417
    Abstract: A semiconductor device package includes a semiconductor device, an optical conductive pillar, a first encapsulant and a second encapsulant. The semiconductor device includes a pixel. The optical conductive pillar is disposed on the pixel. The first encapsulant has a first thickness and encapsulates the optical conductive pillar. The second encapsulant has a second thickness different from the first thickness.
    Type: Application
    Filed: February 27, 2019
    Publication date: August 29, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Yu-Min PENG
  • Publication number: 20190147605
    Abstract: Disclosed is a detection target positioning method and device. The method comprises: acquiring an original image and pre-processing the original image to obtain a gradation of each pixel in a target gradation image corresponding to a target region including a detection target; calculating first gradation sets corresponding to rows of pixels of the target gradation image and second gradation sets corresponding to columns of pixels of the target gradation image; and determining rows of two ends of the detection target in a column direction according to the first gradation sets, determining columns of two ends of the detection target in a row direction according to the second gradation sets, and determining a center of the detection target according to the row of two ends of the detection target in the column direction and the columns of two ends of the detection target in the row direction.
    Type: Application
    Filed: November 7, 2018
    Publication date: May 16, 2019
    Inventors: Fuyin WANG, Ruoyu HUANG, Min PENG, Yue LI
  • Publication number: 20190101998
    Abstract: An in-cell touch array substrate, a driving method thereof, and a display device are provided. The in-cell touch array substrate includes a common electrode layer. The common electrode layer includes: pixel-related common electrodes corresponding to all pixel regions of the in-cell touch array substrate and configured to, at a touch stage, receive a common electrode signal; and shielding common electrodes corresponding to at least a part of a non-pixel region outside all the pixel regions and configured to, at the touch stage, receive a touch sensing signal.
    Type: Application
    Filed: January 10, 2017
    Publication date: April 4, 2019
    Applicant: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Min PENG, Hong WANG, Yaoqiu JING
  • Patent number: D865812
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: November 5, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eujin L. Park, Kim Im, Min Peng
  • Patent number: D881942
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: April 21, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eujin L. Park, Kim Im, Min Peng