Abstract: The present disclosure relates to a medical system, comprising at least an implantable medical device, and a multi-axis accelerometer comprised by the implantable medical device for measuring an acceleration of the implantable medical device along a plurality of vectors, wherein the multi-axis accelerometer is configured to provide for each vector a signal indicative of the acceleration of the implantable medical device in the direction of the respective vector. The medical system is configured to assess said signals to automatically select or propose a vector of said plurality of vectors that comprises the best alignment with a pre-defined vector.

Abstract: A pacemaker comprises a processing unit, a detector and a pacing signal generator, all electrically interconnected, the detector determines patient activity signals and provides the activity signals to the processing unit, the processing unit determines a pacing rate based on the currently received activity signals and on a gain value in an adaption or stabilized mode, the processing unit produces a pace control signal based on the determined pacing rate and provides it to the pacing signal generator, in the adaption mode the processing unit adapts the gain value to the specific patient, the processing unit stays in the adaption mode as long as a stability criterion is not met and transitions in the stabilized mode if a stability criterion is met, wherein in the stabilized mode the processing unit uses a locked gain value determined based on the most recently adapted gain values for determining the pacing rate.

Abstract: An imaging device includes a pixel array of pixel circuits arranged in rows and columns. Bitlines are coupled to the pixel circuits. Clamp circuits are coupled to the bitlines. Each of the clamp circuits includes a clamp short transistor to a power line and a respective one of the bitlines. The clamp short transistor is configured to be switched in response to a clamp short enable signal. A first diode drop device is coupled to the power line. A clamp idle transistor is coupled to the first diode drop device such that the first diode drop device and the clamp idle transistor are coupled between the power line and the respective one of the bitlines. The clamp idle transistor is configured to be switched in response to a clamp idle enable signal.

Abstract: A communication system for establishing an intra-body communication comprises a multiplicity of implantable medical devices, each of the multiplicity of implantable medical devices comprising communication circuitry for communicating with another of the multiplicity of implantable medical devices using a first signaling technique. At least one external device comprises first communication circuitry for communicating with the multiplicity of implantable medical devices using said first signaling technique and second communication circuitry for communicating with a remote system using a second signaling technique different than the first signaling technique.

Abstract: An implantable cardiac pacemaker, wherein the pacemaker is configured to apply pacing pulses to the heart of a person during operation of the pacemaker, and wherein the pacemaker comprises a motion detection system that comprises a first module and a second module. The first module is configured to continuously run during operation of the pacemaker. The second module is configured to receive a trigger signal to change from an idle state to an active state or to receive a further trigger signal to change from an active state to an idle state. An energy consumption per time unit of the second module in the active state is larger than in the idle state. When the second module is in its active state, the second module is configured to execute a rate adaptation algorithm that adapts a rate of the pacing pulses to meet a metabolic demand of the person.

Abstract: An intra-body network system, comprises a first implantable medical device comprising a first communication circuitry and a second implantable medical device comprising a second communication circuitry. The first and second communication circuitries are configured to establish, in an implanted state of the first and second implantable medical devices, a communication for transmitting a communication signal from the first implantable medical device to the second implantable medical device and from the second implantable medical device to the first implantable medical device.

Abstract: In an embodiment, a method of reducing resistance-capacitance delay along photodiode transfer lines of an image sensor includes forking a plurality of photodiode transfer lines each into a plurality of sublines coupled together and to a first decoder-driver at a first end of each subline; and distributing selection transistors of a plurality of multiple-photodiode cells among the plurality of sublines. In embodiments, the sublines may be recombined at a second end of the sublines and driven by a second decoder-driver at the second end.

Abstract: An imaging device includes a pixel array of pixel circuits arranged in rows and columns. Bitlines are coupled to the pixel circuits. Clamp circuits are coupled to the bitlines. Each of the clamp circuits includes a clamp short transistor to a power line and a respective one of the bitlines. The clamp short transistor is configured to be switched in response to a clamp short enable signal. A first diode drop device is coupled to the power line. A clamp idle transistor is coupled to the first diode drop device such that the first diode drop device and the clamp idle transistor are coupled between the power line and the respective one of the bitlines. The clamp idle transistor is configured to be switched in response to a clamp idle enable signal.

Abstract: In an embodiment, a method of reducing resistance-capacitance delay along photodiode transfer lines of an image sensor includes forking a plurality of photodiode transfer lines each into a plurality of sublines coupled together and to a first decoder-driver at a first end of each subline; and distributing selection transistors of a plurality of multiple-photodiode cells among the plurality of sublines. In embodiments, the sublines may be recombined at a second end of the sublines and driven by a second decoder-driver at the second end.

Abstract: An imaging device includes a pixel array of 1×3 pixel circuits that include 3 photodiodes in a column. Bitlines are coupled to the 1×3 pixel circuits. The bitlines are divided into groupings of 3 bitlines per column of the 1×3 pixel circuits. Each column of the 1×3 pixel circuits includes a plurality of first banks coupled to a first bitline, a plurality of second banks coupled to a second bitline, and a plurality of third banks coupled to a third bitline of a respective grouping of the 3 bitlines. The 1×3 pixel circuits are arranged into groupings of 3 1×3 pixel circuits per nine cell pixel structures that form a plurality of 3×3 pixel structures of the pixel array.

Abstract: An image sensor includes an array of multiple-photodiode cells, each photodiode coupled through a selection transistor to a floating diffusion of the cell, the selection transistors controlled by respective transfer lines, a reset, a sense source follower, and a read transistor coupled from the source follower to a data line. The array includes phase detection rows with phase detection cells and normal cells; and a compensation row of more cells. In embodiments, each phase detection row has cells with at least one photodiode coupled to the floating diffusion by selection transistors controlled by a transfer line separate from transfer lines of selection transistors of adjacent normal cells of the row. In embodiments, the compensation row has cells with photodiodes coupled to the floating diffusion by selection transistors controlled by a transfer line separate from transfer lines of selection transistors of adjacent normal cells of the compensation row.

Abstract: An arithmetic logic unit (ALU) includes a front end latch stage coupled to latch Gray code (GC) outputs of a GC generator in response to a comparator output. A signal latch stage is coupled to latch outputs of the front end latch stage. A GC to binary stage is coupled to generate a binary representation of the GC outputs latched in the signal latch stage. First inputs of an adder stage are coupled to receive outputs of the GC to binary stage. Outputs of the adder stage are generated in response to the first inputs and second inputs of the adder stage. A pre-latch stage is coupled to latch outputs of the adder stage. A feedback latch stage is coupled to latch outputs of the pre-latch stage. The second inputs of the adder stage are coupled to receive outputs of the feedback latch stage.

Abstract: A ramp generator providing ramp signal with high resolution fine gain includes a current mirror having a first and second paths to conduct a capacitor current and an integrator current responsive to the capacitor current. First and second switched capacitor circuits are coupled to the first path. A fractional divider circuit is coupled to receive a clock signal to generate in response to an adjustable fractional divider ratio K a switched capacitor control signal that oscillates between first and second states to control the first and second switched capacitor circuits. The first and second switched capacitor circuits are coupled to be alternatingly charged by the capacitor current and discharged in response to each the switched capacitor control signal. An integrator coupled is to the second path to generate the ramp signal in response to the integrator current.

Abstract: An intracardiac pacemaker device, comprising a housing that is configured to be implanted entirely within a ventricle (V) of a heart (H), an electronic module for generating pacing pulses, a battery for supplying energy to the electronic module, an elongated lead extension protruding from the housing, at least a first electrode arranged on the elongated lead extension, and a pacing electrode and a return electrode for applying the pacing pulses to cardiac tissue, wherein the pacing electrode is arranged on the housing. The electronic module is electrically coupled to the pacing electrode via the housing, and wherein the electronic module is configured to carry out measurements of electrical activity via the at least one first electrode of the elongated lead extension.

Abstract: A clock control circuit of an ADC includes a plurality of fractional divider circuits, each including a programmable integer divider coupled to receive an enable skew signal, a clock signal, and an output integer signal to divide down the clock signal by a factor responsive to the output integer signal to generate a fractional divider signal. A delta-sigma modulator is coupled to receive a fractional modulus signal, an input integer signal, and the fractional divider signal to generate the output integer signal, which is a varying signal each cycle and having a long term average DC value substantially equal to a fractional divider ratio K. An extended gain control circuit is coupled to receive the fractional divider signal from each of the fractional divider circuits to generate a plurality of ramp clock signals with adjustable frequencies to adjust a gain setting of a ramp generator of the ADC.

Abstract: A readout circuit for use in an image sensor includes a plurality of comparators. Each one of the plurality of comparators is coupled to receive a ramp signal and a respective analog image data signal from a respective one of a plurality of column bit lines to generate a respective comparator output. Each one of a plurality of arithmetic logic units (ALUs) is coupled to receive phase-aligned Gray code (GC) outputs generated by a GC generator. Each one of the plurality of ALUs is further coupled to a respective one of the plurality of comparators to receive the respective comparator output. Each one of the plurality of ALUs is coupled to latch the phase-aligned GC outputs in response to the respective comparator output to generate a respective digital image data signal.

Abstract: An arithmetic logic unit (ALU) includes a front end latch stage coupled to latch Gray code (GC) outputs of a GC generator in response to a comparator output. A signal latch stage is coupled to latch outputs of the front end latch stage. A GC to binary stage is coupled to generate a binary representation of the GC outputs latched in the signal latch stage. First inputs of an adder stage are coupled to receive outputs of the GC to binary stage. Outputs of the adder stage are generated in response to the first inputs and second inputs of the adder stage. A pre-latch stage is coupled to latch outputs of the adder stage. A feedback latch stage is coupled to latch outputs of the pre-latch stage. The second inputs of the adder stage are coupled to receive outputs of the feedback latch stage.

Abstract: The present disclosure relates to a medical system, comprising at least an implantable medical device, and a multi-axis accelerometer comprised by the implantable medical device for measuring an acceleration of the implantable medical device along a plurality of vectors, wherein the multi-axis accelerometer is configured to provide for each vector a signal indicative of the acceleration of the implantable medical device in the direction of the respective vector. The medical system is configured to assess said signals to automatically select or propose a vector of said plurality of vectors that comprises the best alignment with a pre-defined vector.

Abstract: An image sensor includes a pixel array with active rows of pixel cells, a black level calibration row with black image data generation circuits coupled to generate black image data signals representative of an absence of the incident light, and a dummy row with black level clamping circuits coupled to receive a black sun reference voltage to clamp bitlines of the pixel array, and a black level calibration circuit coupled to receive the black sun reference voltage to generate a black sun calibration voltage. A black sun feedback circuit is coupled to generate the black sun reference voltage in response to the black sun calibration voltage and a black level sample reference, and a black level sampling circuit is coupled to the bitlines to sample the black image data signals to generate the black level sample reference received by the black sun feedback circuit.

Abstract: An implantable cardiac pacemaker, wherein the pacemaker is configured to apply pacing pulses to the heart of a person during operation of the pacemaker, and wherein the pacemaker comprises a motion detection system that comprises a first module and a second module. The first module is configured to continuously run during operation of the pacemaker. The second module is configured to receive a trigger signal to change from an idle state to an active state or to receive a further trigger signal to change from an active state to an idle state. An energy consumption per time unit of the second module in the active state is larger than in the idle state. When the second module is in its active state, the second module is configured to execute a rate adaptation algorithm that adapts a rate of the pacing pulses to meet a metabolic demand of the person.