Abstract: A semiconductor device includes a bank address generation circuit, a row/column address generation circuit, and an operation control circuit. The bank address generation circuit generates a bank address signal according to a bank group selection signal which is generated in response to a first temperature code and a second temperature code. The row/column address generation circuit generates a row address signal and a column address signal according to an area selection signal which is generated in response to a third temperature code and a fourth temperature code. The operation control circuit performs a data scrub operation on a cell which is accessed by the bank address signal, the row address signal and the column address signal.

Abstract: A refresh control device may include, an address processing circuit configured to divide an input address into a plurality of partial addresses, and generate an updated partial address input count based on an input count for each partial address value. The refresh control device also includes a target refresh address generation circuit configured to generate a target refresh address based on the updated partial address input count, and a target refresh circuit configured to perform a refresh operation on a word line corresponding to the target refresh address.

Abstract: Provided are a system and a method for guiding a result of remote control using a mobile device, and particularly, a system and a method for guiding a result of remote control, which determines a scheme that feeds back the remote control result of a vehicle to a mobile device app of a user.

Abstract: Disclosed is a stopper and a container having the same including a stopper body including an upper part having a discharge hole, and a side part, having at least a dual structure, including an inner part and an external part which are spaced apart from each other and a coupling portion coupling the inner part and the external part at a top of the inner part and the external part, wherein the side part may include a first protrusion at the top of the inner part, a first groove at the coupling portion and a second protrusion between the first groove and the external part.

Abstract: A container cap according to the present invention includes a lower cap combined with a container and comprising an opening communicating with an inside of the container; and an upper cap combined with the lower cap to cover the opening. Further, the upper cap includes a cover covering the opening; a rim provided around the cover and partly connected to the cover; a connection part connecting the rim and the cover; and a handle connected to the rim and having a round shape, which curves outwards from a center of the cover, viewed on a plane.

Abstract: An anti-reflective film includes a transparent substrate, and a high hardness coating layer on at least one surface of the transparent substrate, the high hardness coating layer having a hardness of about 4H or higher and a moth-eye pattern.

Abstract: Internal voltage generation circuits are provided. The internal voltage generation circuit includes a code signal generator and an internal voltage generator. The code signal generator generates input code signals having a logic level combination corresponding to a difference between a frequency of an external clock signal and a frequency of an internal clock signal. The internal voltage generator is selectively activated according to the logic level combination of the input code signals to drive an internal voltage signal.

Abstract: Example embodiments relate to a manufacturing device of an anti-reflecting structure and a method for manufacturing the anti-reflecting structure. The manufacturing device of an anti-reflecting structure includes a carrier film on which a stamp structure is formed, an unwinding unit which unwinds the carrier film, a substrate support unit which provides a target substrate to the carrier film, a pressing unit which applies pressure to the carrier film so that a resin provided in the stamp structure is provided to the target substrate, and a winding unit which winds the carrier film from which an anti-reflecting pattern is transferred to the target substrate, wherein the pressing unit includes a chamber which stores the target substrate, and a vent hole formed in the chamber, and air within the chamber is discharged through the vent hole to lower the air pressure in the chamber and apply pressure to the carrier film.

Abstract: Disclosed is a stopper and a container having the same including a stopper body including an upper part having a discharge hole, and a side part, having at least a dual structure, including an inner part and an external part which are spaced apart from each other and a coupling portion coupling the inner part and the external part at a top of the inner part and the external part, wherein the side part may include a first protrusion at the top of the inner part, a first groove at the coupling portion and a second protrusion between the first groove and the external part.

Abstract: A power control apparatus of an energy storage system and method of controlling the power control apparatus are provided. The power control apparatus includes a battery manager to monitor a charge state of at least one battery module and to manage charge and discharge of the at least one battery module, a power converter to convert power of the at least one battery module from alternating current (AC) to direct current (DC) or from DC to AC, a controller configured to control the battery manager and the power converter, and a standby power supplier configured to supply constant power to the battery manager, the power converter, and the controller when the battery manager is not driven.

Abstract: A memory system includes a memory controller suitable for generating process skew information thereof, and a semiconductor memory device suitable for controlling an operation of an internal circuit based on the process skew information.

Abstract: An internal voltage generating circuit capable of controlling a swing width of a detection signal in a semiconductor memory apparatus is provided. The internal voltage generating circuit of a semiconductor memory apparatus includes an internal voltage level detecting unit configured to compare an internal voltage with a target voltage and then generate a detection signal, and an internal voltage level control unit configured to control the internal voltage based on a voltage level of the detection signal, wherein the internal voltage level detecting unit is configured to control a swing width of the detection signal based on a voltage difference between the internal voltage and the target voltage.

Abstract: Internal voltage generation circuits are provided. The internal voltage generation circuit includes a code signal generator and an internal voltage generator. The code signal generator generates input code signals having a logic level combination corresponding to a difference between a frequency of an external clock signal and a frequency of an internal clock signal. The internal voltage generator is selectively activated according to the logic level combination of the input code signals to drive an internal voltage signal.

Abstract: Internal voltage generation circuits are provided. The internal voltage generation circuit includes a code signal generator and an internal voltage generator. The code signal generator generates input code signals having a logic level combination corresponding to a difference between a frequency of an external clock signal and a frequency of an internal clock signal. The internal voltage generator is selectively activated according to the logic level combination of the input code signals to drive an internal voltage signal.

Abstract: A semiconductor apparatus includes a signal transmission block and signal reception blocks. The signal transmission block is disposed in a first chip and configured to transmit fuse information in synchronization with transmission control signals. The signal reception blocks are respectively disposed in the first chip and a second chip and configured to receive the fuse information in synchronization with reception control signals.

Abstract: An internal voltage generating circuit capable of controlling a swing width of a detection signal in a semiconductor memory apparatus is provided. The internal voltage generating circuit of a semiconductor memory apparatus includes an internal voltage level detecting unit configured to compare an internal voltage with a target voltage and then generate a detection signal, and an internal voltage level control unit configured to control the internal voltage based on a voltage level of the detection signal, wherein the internal voltage level detecting unit is configured to control a swing width of the detection signal based on a voltage difference between the internal voltage and the target voltage.

Abstract: An internal voltage generation circuit includes a flag signal generator suitable for generating a first flag signal which is enabled after a first predetermined time from a moment that a deep power-down mode terminates and suitable for generating a second flag signal which is enabled after a second predetermined time from a moment that the first flag signal is enabled, a drive signal generator suitable for receiving the first and second flag signals to generate a first drive signal and a second drive signal and suitable for receiving a pre-oscillation signal in response to the first and second flag signals to generate a third drive signal and a fourth drive signal, and an internal voltage generator suitable for driving a first internal voltage signal in response to the first and second drive signals and suitable for pumping a second internal voltage signal in response to the third and fourth drive signals.

Abstract: Internal voltage generation circuits are provided. The internal voltage generation circuit includes a code signal generator and an internal voltage generator. The code signal generator generates input code signals having a logic level combination corresponding to a difference between a frequency of an external clock signal and a frequency of an internal clock signal. The internal voltage generator is selectively activated according to the logic level combination of the input code signals to drive an internal voltage signal.

Abstract: An internal voltage generating circuit capable of controlling a swing width of a detection signal in a semiconductor memory apparatus is provided. The internal voltage generating circuit of a semiconductor memory apparatus includes an internal voltage level detecting unit configured to compare an internal voltage with a target voltage and then generate a detection signal, and an internal voltage level control unit configured to control the internal voltage based on a voltage level of the detection signal, wherein the internal voltage level detecting unit is configured to control a swing width of the detection signal based on a voltage difference between the internal voltage and the target voltage.

Abstract: Disclosed is a composition including a pyrazino-triazine derivative and a pharmaceutically acceptable salt thereof. The composition includes a solubilizer or a stabilizer and thus can exhibit very excellent solubility and stability.