Patents by Inventor Min Seong Ryu

Min Seong Ryu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060081849
    Abstract: An organic thin film transistor array panel is provided, which includes: a substrate; a data line formed on the substrate and including a source electrode; a drain electrode formed on the substrate and separated from the data line; an organic semiconductor disposed on the source electrode and the drain electrode; a gate insulator formed on the organic semiconductor; a gate line including a gate electrode disposed on the gate insulator; a passivation layer formed on the gate line and having a first contact hole on the drain electrode; a pixel electrode connected to the drain electrode through the first contact hole; and an opaque light blocking member disposed under the organic semiconductor.
    Type: Application
    Filed: July 20, 2005
    Publication date: April 20, 2006
    Inventors: Yong-Uk Lee, Bo-Sung Kim, Min-Seong Ryu, Mun-Pyo Hong
  • Publication number: 20050287719
    Abstract: A method of manufacturing a thin film transistor array panel includes: forming a gate line on a substrate; forming a gate insulating layer on the gate line; forming a data line and a drain electrode on the gate insulating layer; depositing an organic semiconductor layer on the data line, the drain electrode and exposed portions of the gate insulating layer; depositing a protection layer on the organic semiconductor layer; forming a photoresist on the protection layer, the photoresist having positive photosensitivity; etching the protection layer and the organic semiconductor layer using the photoresist as an etch mask; forming a passivation layer on the protection layer, the data line, and the drain electrode, the passivation layer having a contact hole exposing a portion of the drain electrode; and forming a pixel electrode on the passivation layer, the pixel electrode electrically connected to the drain electrode via the contact hole.
    Type: Application
    Filed: June 2, 2005
    Publication date: December 29, 2005
    Inventors: Min-Seong Ryu, Tae-Young Choi, Yong-Uk Lee, Woo-Jae Lee, Bo-Sung Kim
  • Publication number: 20050274953
    Abstract: A method of manufacturing a thin film transistor array panel is provided, the method includes forming a gate line on a substrate; forming a gate insulating layer on the gate line; forming a data line and a drain electrode on the gate insulating layer; forming an organic semiconductor layer on the data line, the drain electrode and an exposed portion of the gate insulating layer between the data line and the drain electrodel; forming a protective member fully covering the organic semiconductor layer; forming a passivation layer on the protective layer, the data line, and the drain electrode; forming a contact hole in the passivation layer to expose a portion of the drain electrode; and forming a pixel electrode on the passivation layer, the pixel electrode connected to the drain electrode through the contact hole.
    Type: Application
    Filed: June 13, 2005
    Publication date: December 15, 2005
    Inventors: Bo-Sung Kim, Woo-Jae Lee, Min-Seong Ryu
  • Publication number: 20050045885
    Abstract: The present invention disclosed an organic thin film transistor, an organic thin film transistor array substrate and an organic thin film transistor display. The present invention disclosed organic materials which is proper for the application to a large screen display. The presentation also disclosed structures and a method for manufacturing such an organic thin film transistor, the organic thin film transistor array substrate and the organic thin film transistor display.
    Type: Application
    Filed: August 27, 2004
    Publication date: March 3, 2005
    Inventors: Bo Kim, Mun-Pyo Hong, Min-Seong Ryu, Yong-Uk Lee
  • Publication number: 20030007746
    Abstract: Disclosed is a junction device for assembling a PLC (Planar Lightwave Circuit) chip and an optical-fiber block used in an optical-communication system. The junction device includes: an ultraviolet-hardening adhesive filled into a space between the interfaces of the PLC chip and the optical-fiber block, the interfaces being inclined at a given angle; an ultraviolet-light source positioned over the ultraviolet-hardening adhesive for hardening the ultraviolet-hardening adhesive; an optical sensor positioned under the ultraviolet-hardening adhesive for measuring the power changes in the ultraviolet output that have penetrated through the ultraviolet-hardening adhesive; an optical power-meter for displaying the power changes of the ultraviolet based on the data received from the optical sensor; and, a controller for detecting when the ultraviolet-hardening adhesive is completely hardened based on data received from the optical power-meter.
    Type: Application
    Filed: May 7, 2002
    Publication date: January 9, 2003
    Inventors: Min-Seong Ryu, Sang-Yup Song, Tae-Hoon Kim