Patents by Inventor Min Shen

Min Shen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11986246
    Abstract: A method and system are provided to determine an optimal placement with respect to position and orientation for one or more bones in a workspace of a robot to improve robotic cutting and maximize the robot workspace during a robotic surgical procedure. The method is additionally useful to aid a user in positioning and orienting the bones in the operating room at the determined position and orientation.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: May 21, 2024
    Assignee: Think Surgical, Inc.
    Inventors: Jay Roldan, Min Yang Jung, Feimo Shen, Muhammad Afnan, Barry Voorhees, Micah Forstein, CJ Geering, Koteswara Ruvva, Joel Zuhars
  • Patent number: 11990522
    Abstract: A semiconductor structure includes a substrate and a semiconductor channel layer over the substrate. The semiconductor structure includes a high-k gate dielectric layer over the semiconductor channel layer, a work function metal layer over the high-k gate dielectric layer, and a bulk metal layer over the work function metal layer. The work function metal layer includes a first portion and a second portion over the first portion. Both the first portion and the second portion are conductive. Materials included in the second portion are also included in the first portion. The first portion is doped with silicon at a first dopant concentration, and the second portion is not doped with silicon or is doped with silicon at a second dopant concentration lower than the first dopant concentration.
    Type: Grant
    Filed: December 9, 2022
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yen-Tien Tung, Szu-Wei Huang, Zhi-Ren Xiao, Yin-Chuan Chuang, Yung-Chien Huang, Kuan-Ting Liu, Tzer-Min Shen, Chung-Wei Wu, Zhiqiang Wu
  • Publication number: 20240153536
    Abstract: Embodiments of the present disclosure provide a video editing method and apparatus, an electronic device, and a storage medium. The method comprises: creating at least one editing subtask for a video editing task; in response to a first operation for triggering a target editing subtask, obtaining an initial video material and presenting an editing interface of the target editing subtask; recording the editing operation triggered in the editing interface and presenting an indication identifier of the editing operation in the editing track; generating an editing result of the target editing subtask based on the recorded information of the editing operation and the initial video material; based on the editing result of each editing subtask of the video editing task, generating a target video as an editing result of the video editing task.
    Type: Application
    Filed: December 20, 2023
    Publication date: May 9, 2024
    Inventors: Xiaoran Zhang, Yuan Zhang, Xinyi Zha, Zhirui Jiang, Min Shen, Yu Zhang, Yan He, Jiahui Qiu, Shangshang Xiang, Long Ma
  • Patent number: 11963516
    Abstract: A method for depth of field tracking and controlling of a pet companion robot device to interact with a pet includes the steps of: locating a target pet within a field of view of the camera; drawing a minimum target rectangle around the target pet, with sides of the minimum target rectangle parallel with the corresponding sides of the field of view of the camera; locating a center point P of the minimum target rectangle. When P is located in quadrangles I and II, adjusting the pet companion robot device to the right to make P overlap with the vertical center line of the field of view of the camera; and when P is located in quadrangles III and IV, adjusting the pet companion robot device to the left to make P overlap with the vertical center line of the field of view of the camera.
    Type: Grant
    Filed: March 28, 2022
    Date of Patent: April 23, 2024
    Assignee: Pumpkii Inc.
    Inventors: Hao Shen, Xiaomei Shu, Min Zhou
  • Publication number: 20240123647
    Abstract: A fixture assembly for slitting a workpiece into a serpentine body, a cutting system having a fixture assembly, and a method of forming a serpentine body. The fixture assembly includes a patterned support section that has a plurality of support slats interspaced with gaps. A holder plate has an opening configured to receive the workpiece and positioned atop the patterned support section such that intended cutting locations in the workpiece are positioned directly above the gaps in the patterned support section and the slats are positioned directly below uncut portions of the serpentine body after cutting the workpiece.
    Type: Application
    Filed: October 4, 2023
    Publication date: April 18, 2024
    Inventors: Song Lyu, Min Shen
  • Publication number: 20240128454
    Abstract: A negative electrode plate, a battery, and a battery pack are provided. The negative electrode plate includes a negative current collector and a negative material layer disposed on a surface of the negative current collector. The negative material layer includes a hard carbon material containing primary particles and secondary particles, and the primary particles have a defect value different from that of the secondary particles. In comparison with the solution of only using one kind of hard carbon particles having the same defect value as the negative material layer, the negative electrode plate of the present disclosure includes two kinds of hard carbon particles with different defect values, which combines the excellent properties of the two kinds of hard carbon particles. Therefore the negative electrode plate has excellent properties while satisfying the requirements of a battery, such as high energy density, high first-cycle discharge efficiency, and excellent rate performance.
    Type: Application
    Filed: December 7, 2023
    Publication date: April 18, 2024
    Inventors: Yingxin LIN, Liuxue SHEN, Jiaqi WEN, Min ZHANG
  • Publication number: 20240108978
    Abstract: A remote display synchronization technique preserves the presence of a local display device for a remotely-rendered video stream. A server and a client device cooperate to dynamically determine a target frame rate for a stream of rendered frames suitable for the current capacities of the server and the client device and networking conditions. The server generates from this target frame rate a synchronization signal that serves as timing control for the rendering process. The client device may provide feedback to instigate a change in the target frame rate, and thus a corresponding change in the synchronization signal. In this approach, the rendering frame rate and the encoding frequency may be “synchronized” in a manner consistent with the capacities of the server, the network, and the client device, resulting in generation, encoding, transmission, decoding, and presentation of a stream of frames that mitigates missed encoding of frames while providing acceptable latency.
    Type: Application
    Filed: September 29, 2022
    Publication date: April 4, 2024
    Inventors: Jeffrey G. Cheng, Yuping Shen, Mikhail Mironov, Min Zhang
  • Patent number: 11942134
    Abstract: A memory circuit includes a memory array including a plurality of memory cells, each memory cell of the plurality of memory cells including an n-type channel layer including a metal oxide material, and a gate structure overlying and adjacent to the n-type channel layer, the gate structure including a conductive layer overlying a ferroelectric layer. The memory circuit is configured to apply a gate voltage to each memory cell of the plurality of memory cells in first and second write operations, the gate voltage has a positive polarity and a first magnitude in the first write operation and a negative polarity and a second magnitude greater than the first magnitude in the second write operation.
    Type: Grant
    Filed: November 18, 2022
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Huan-Sheng Wei, Tzer-Min Shen, Zhiqiang Wu
  • Publication number: 20240097011
    Abstract: A method includes forming a fin structure over a substrate, wherein the fin structure comprises first semiconductor layers and second semiconductor layers alternately stacked over a substrate; forming a dummy gate structure over the fin structure; removing a portion of the fin structure uncovered by the dummy gate structure; performing a selective etching process to laterally recess the first semiconductor layers, including injecting a hydrogen-containing gas from a first gas source of a processing tool to the first semiconductor layers and the second semiconductor layers; and injecting an F2 gas from a second gas source of the processing tool to the first semiconductor layers and the second semiconductor layers; forming inner spacers on opposite end surfaces of the laterally recessed first semiconductor layers of the fin structure; and replacing the dummy gate structure and the first semiconductor layers with a metal gate structure.
    Type: Application
    Filed: December 1, 2023
    Publication date: March 21, 2024
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY LIMITED
    Inventors: Han-Yu LIN, Fang-Wei LEE, Kai-Tak LAM, Raghunath PUTIKAM, Tzer-Min SHEN, Li-Te LIN, Pinyen LIN, Cheng-Tzu YANG, Tzu-Li LEE, Tze-Chung LIN
  • Publication number: 20240067566
    Abstract: A method for preparing Portland cement includes: respectively weighing iron slag, copper slag, vanadium slag, and nickel slag and grinding, to yield prefabricated iron slag, prefabricated copper slag, prefabricated vanadium slag, and prefabricated nickel slag; weighing mica and kaolinite, mixing, and grinding to obtain aluminous raw materials; evenly mixing the prefabricated iron slag and the aluminous raw materials, and calcining, to yield an iron-aluminum eutectic mineral; weighing the marble, fluorite, dolomite, and quartz, evenly mixing the marble, fluorite, dolomite, and quartz with the prefabricated copper slag, prefabricated vanadium slag, and prefabricated nickel slag to yield a first mixture; grinding the iron-aluminum eutectic mineral to yield powders, and calcining a second mixture of the first mixture and the powders, to yield the cement clinker; and cooling the cement clinker, and grinding a third mixture of the cooled cement clinker and the gypsum, to yield the Portland cement.
    Type: Application
    Filed: May 11, 2023
    Publication date: February 29, 2024
    Inventors: Kunyue ZHANG, Xiao ZHI, Min WANG, Zhaijun WEN, Xiaopeng AN, Wen HUANG, Guang YAO, Yang YU, Xin SHEN
  • Patent number: 11912770
    Abstract: Provided are a single-domain antibody against human programmed death-ligand 1 (PD-L1) and application thereof. The PD-L1 binding molecule of the present invention can be used for treating and/or preventing, or diagnosing PD-L1 related diseases such as tumors.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: February 27, 2024
    Assignee: SHANGHAI NOVAMAB BIOPHARMACEUTICALS CO., LTD.
    Inventors: Yakun Wan, Min Zhu, Xiaoning Shen, Junwei Gai
  • Patent number: 11916471
    Abstract: An example electronic device includes a controller to determine a user touch detection by a power adaptor coupled to the electronic device to operate the electronic device in an AC power mode. The power adaptor may comprise a proximity sensor to detect a user touch for detachment of the power adaptor from the electronic device, and a control circuit to operate a configuration pin in a low output mode to signal user touch detection. The controller may initiate central processing unit (CPU) throttling to reduce power consumption by the electronic device. The controller may further stop CPU throttling in response to detecting that the power adaptor has been detached from the electronic device. Further, the controller may switch the electronic device to a DC power mode to operate using DC power supplied by a battery of the electronic device in response to power adaptor detachment.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: February 27, 2024
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Ting-Yang Tsai, Yi-Chen Chen, Ching-Lung Wang, Yu-Min Shen
  • Publication number: 20240063263
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first nanostructure over the substrate. The first nanostructure has a (001) surface, the first nanostructure has a first channel direction on the (001) surface, and the first channel direction is [0 1 0] or [0 ?1 0]. The semiconductor device structure includes a gate stack surrounding the first nanostructure. The semiconductor device structure includes a first source/drain structure and a second source/drain structure over the substrate and over opposite sides of the gate stack. The first nanostructure is between the first source/drain structure and the second source/drain structure, and the first channel direction is from the first source/drain structure to the second source/drain structure.
    Type: Application
    Filed: November 2, 2023
    Publication date: February 22, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Huang-Siang LAN, Sathaiya Mahaveer DHANYAKUMAR, Tzer-Min SHEN, Zhiqiang WU
  • Patent number: 11894461
    Abstract: A semiconductor device includes a semiconductor substrate, an interfacial layer formed on the semiconductor substrate, a high-k dielectric layer formed on the interfacial layer, and a conductive gate electrode layer formed on the high-k dielectric layer. At least one of the high-k dielectric layer and the interfacial layer is doped with: a first dopant species, a second dopant species, and a third dopant species. The first dopant species and the second dopant species form a plurality of first dipole elements having a first polarity. The third dopant species forms a plurality of second dipole elements having a second polarity, and the first and second polarities are opposite.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: February 6, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiang-Pi Chang, Yen-Tien Tung, Dawei Heh, Chung-Liang Cheng, I-Ming Chang, Yao-Sheng Huang, Tzer-Min Shen, Huang-Lin Chao
  • Publication number: 20240021709
    Abstract: A semiconductor device includes a channel layer, an interfacial layer, a gate dielectric layer, a gate electrode, dipole elements, and additional elements. The interfacial layer is disposed on the channel layer, and includes an insulating material. The gate dielectric layer is disposed over the interfacial layer such that the channel layer is separated from the gate dielectric layer by the interfacial layer. The gate electrode is disposed on the gate dielectric layer. The dipole elements are present in at least one of the interfacial layer and the gate dielectric layer in a predetermined amount such that the semiconductor device has a predetermined threshold voltage. The additional elements are located at a region where the dipole elements are present so as to reduce interfacial defects caused by the dipole elements. The additional elements are different from the dipole elements. Methods for manufacturing the semiconductor device are also disclosed.
    Type: Application
    Filed: July 15, 2022
    Publication date: January 18, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chansyun David YANG, Huang-Lin CHAO, Hsiang-Pi CHANG, Yen-Tien TUNG, Chung-Liang CHENG, Yu-Chia LIANG, Shen-Yang LEE, Yao-Sheng HUANG, Tzer-Min SHEN, Pinyen LIN
  • Publication number: 20240017299
    Abstract: Described herein is a method for removing deposits off a surface of a chamber component. The method includes receiving a chamber component, and fixing the chamber component in a fixture. A slurry is then applied to a surface of the chamber component, where the slurry has a pH of about 5 to about 9. The surface is then polished using a polish pad and the slurry. The surface roughness of the surface after polishing is within about 10% of the surface roughness before polishing, and wherein deposits on the surface of the chamber component are removed by polishing. An alternative method for removing deposits is also presented, wherein the chamber component is heated to a temperature of about 500° C. to about 1500° C.
    Type: Application
    Filed: July 12, 2022
    Publication date: January 18, 2024
    Inventors: Tuochuan Huang, Min Shen, Kenneth Chien, Han Wang, Stayce Parmer, Rynn Wang
  • Patent number: 11855192
    Abstract: A method includes forming a fin structure including a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked over a substrate. A dummy gate structure is formed across the fin structure. The exposed second portions of the fin structure are removed. A selective etching process is performed, using a gas mixture including a hydrogen-containing gas and a fluorine-containing gas, to laterally recess the first semiconductor layers. Inner spacers are formed on opposite end surfaces of the laterally recessed first semiconductor layers. Source/drain epitaxial structures are formed on opposite end surfaces of the second semiconductor layers. The dummy gate structure is removed to expose the first portion of the fin structure. The laterally recessed first semiconductor layers are removed. A gate structure is formed to surround each of the second semiconductor layers.
    Type: Grant
    Filed: January 19, 2021
    Date of Patent: December 26, 2023
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY LIMITED
    Inventors: Han-Yu Lin, Fang-Wei Lee, Kai-Tak Lam, Raghunath Putikam, Tzer-Min Shen, Li-Te Lin, Pinyen Lin, Cheng-Tzu Yang, Tzu-Li Lee, Tze-Chung Lin
  • Publication number: 20230411399
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first fin active region of a first semiconductor material disposed within the first region, oriented in a first direction, wherein the first fin active region has a <100> crystalline direction along the first direction; and a second fin active region of a second semiconductor material disposed within the second region and oriented in the first direction, wherein the second fin active region has a <110> crystalline direction along the first direction.
    Type: Application
    Filed: July 20, 2023
    Publication date: December 21, 2023
    Inventors: Tzer-Min Shen, Zhiqiang Wu, Chung-Cheng Wu, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang, Min Cao
  • Publication number: 20230398716
    Abstract: An extrusion die (16) including a plurality of pins (38) having side surfaces defining an intersecting array of slots (30) extending axially into the die (16) from a discharge face (34) of the die (16). A plurality of feedholes (28) extend axially from an inlet face (32) of the die (16) opposite to the discharge face (34). The feedholes (28) connect with the slots (30) at intersections (35) within the die (16) to create a flow path from the inlet face (32) to the discharge face (34). A first coating (42) is on at least a portion of the feedholes (28) in a first zone (46) extending over a first axial length of the flow path. A second coating (44) that is different than the first coating (42) is on at least a portion of the side surfaces (37) of the pins (38) in a second zone (48) extending over a second axial length of the flow path. Methods of fabricating an extrusion die (16) and manufacturing a ceramic article (100), such as a honeycomb body, are also disclosed.
    Type: Application
    Filed: November 22, 2021
    Publication date: December 14, 2023
    Inventors: Thomas William Brew, Keith Norman Bubb, Ryan Joseph Grohsmeyer, Michael James Lehman, Kenneth Charles Sariego, Min Shen
  • Patent number: 11843032
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first nanostructure over the substrate. The first nanostructure has a first channel direction, and the first channel direction is [1 0 0], [?1 0 0], [0 1 0], or [0 ?1 0]. The semiconductor device structure includes a gate stack over the substrate and surrounding the first nanostructure. The semiconductor device structure includes a first source/drain structure and a second source/drain structure over the substrate and over opposite sides of the gate stack.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: December 12, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Huang-Siang Lan, Sathaiya Mahaveer Dhanyakumar, Tzer-Min Shen, Zhiqiang Wu