Abstract: A wet etching chemistry to selectively remove a polymer residue on an opening embedded in a low-k dielectric layer and an underlying stop layer in a process of forming an interconnect structure is provided. The wet etching chemistry includes: two type of organic solvents, wherein a concentration of the two type of organic solvents is greater than or equal to 70%; an Alkali source amine, at least comprising a tertiary amine; an inhibitor; and water. In some embodiment, the wet etching chemistry is free of a peroxide to avoid damage to the WdC hard mask.

Abstract: A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The semiconductor device includes first and second gate structures disposed on first and second fin structures, first and second source/drain (S/D) regions disposed on the first and second fin structures, first and second contact structures disposed on the first and second S/D regions, and a dipole layer disposed at an interface between the first nWFM silicide layer and the first S/D region. The first contact structure includes a first nWFM silicide layer disposed on the first S/D region and a first contact plug disposed on the first nWFM silicide layer. The second contact structure includes a pWFM silicide layer disposed on the second S/D region, a second nWFM silicide layer disposed on the pWFM silicide layer, and a second contact plug disposed on the pWFM silicide layer.

Abstract: A memory circuit includes a plurality of memory cells, each memory cell of the plurality of memory cells including a gate electrode, a ferroelectric layer adjacent to the gate electrode, a channel layer adjacent to the ferroelectric layer, the channel layer including indium gallium zinc oxide (IGZO), and source and drain contacts adjacent to the channel layer opposite the ferroelectric layer. The memory circuit is configured to, during write operations to a memory cell of the plurality of memory cells, apply a plurality of voltage levels to the gate electrode relative to a ground voltage level applied to the source and drain contacts, a first voltage level of the plurality of voltage levels has a positive polarity and a first magnitude, and a second voltage level of the plurality of voltage levels has a negative polarity and a second magnitude greater than the first magnitude.

Abstract: A honeycomb extrusion die (120) with improved wear properties. Extrusion die has a die body (121) with inlet (122) and exit (123) faces, feedholes (124) with feedhole entrances (124A) and outlets (124B), and a plurality of die pins (126) having side surfaces (128) configured to define a matrix of intersecting slots (130). At least some of the intersecting slots and die pins define a slot structure with divots (132) formed in the side surfaces of the die pins between the feedholes and the exit face, entrance slot portions between the feedhole outlets and the divots, the entrance slot portions having an entrance slot width WA, and exit slot portions between the divots and the exit face, the exit slot portions having an exit slot width WB, wherein WA>WB over an entire slot length. Methods of manufacturing honeycomb structures using the honeycomb extrusion dies and of fabricating the extrusion dies are provided as are other aspects.

Abstract: A semiconductor device includes a substrate, an interfacial layer formed on the semiconductor substrate, and a high-k dielectric layer formed on the interfacial layer. At least one of the high-k dielectric layer and the interfacial layer is doped with: a first dopant species, a second dopant species, and a third dopant species. The first dopant species and the second dopant species form a plurality of first dipole elements having a first polarity. The third dopant species forms a plurality of second dipole elements having a second polarity. A first concentration ratio of the first concentration of the first dopant species to the second concentration of the second dopant species of the p-type transistor is different from a second concentration ratio of the first concentration of the first dopant species to the second concentration of the second dopant species of the n-type transistor.

Abstract: A semiconductor structure includes a substrate and a semiconductor channel layer over the substrate. The semiconductor structure includes a high-k gate dielectric layer over the semiconductor channel layer, a work function metal layer over the high-k gate dielectric layer, and a bulk metal layer over the work function metal layer. The work function metal layer includes a first portion and a second portion over the first portion. Both the first portion and the second portion are conductive. Materials included in the second portion are also included in the first portion. The first portion is doped with silicon at a first dopant concentration, and the second portion is not doped with silicon or is doped with silicon at a second dopant concentration lower than the first dopant concentration.

Abstract: Embodiments of the present disclosure provide a video editing method and apparatus, an electronic device, and a storage medium. The method comprises: creating at least one editing subtask for a video editing task; in response to a first operation for triggering a target editing subtask, obtaining an initial video material and presenting an editing interface of the target editing subtask; recording the editing operation triggered in the editing interface and presenting an indication identifier of the editing operation in the editing track; generating an editing result of the target editing subtask based on the recorded information of the editing operation and the initial video material; based on the editing result of each editing subtask of the video editing task, generating a target video as an editing result of the video editing task.

Abstract: A fixture assembly for slitting a workpiece into a serpentine body, a cutting system having a fixture assembly, and a method of forming a serpentine body. The fixture assembly includes a patterned support section that has a plurality of support slats interspaced with gaps. A holder plate has an opening configured to receive the workpiece and positioned atop the patterned support section such that intended cutting locations in the workpiece are positioned directly above the gaps in the patterned support section and the slats are positioned directly below uncut portions of the serpentine body after cutting the workpiece.

Abstract: A memory circuit includes a memory array including a plurality of memory cells, each memory cell of the plurality of memory cells including an n-type channel layer including a metal oxide material, and a gate structure overlying and adjacent to the n-type channel layer, the gate structure including a conductive layer overlying a ferroelectric layer. The memory circuit is configured to apply a gate voltage to each memory cell of the plurality of memory cells in first and second write operations, the gate voltage has a positive polarity and a first magnitude in the first write operation and a negative polarity and a second magnitude greater than the first magnitude in the second write operation.

Abstract: A method includes forming a fin structure over a substrate, wherein the fin structure comprises first semiconductor layers and second semiconductor layers alternately stacked over a substrate; forming a dummy gate structure over the fin structure; removing a portion of the fin structure uncovered by the dummy gate structure; performing a selective etching process to laterally recess the first semiconductor layers, including injecting a hydrogen-containing gas from a first gas source of a processing tool to the first semiconductor layers and the second semiconductor layers; and injecting an F2 gas from a second gas source of the processing tool to the first semiconductor layers and the second semiconductor layers; forming inner spacers on opposite end surfaces of the laterally recessed first semiconductor layers of the fin structure; and replacing the dummy gate structure and the first semiconductor layers with a metal gate structure.

Abstract: An example electronic device includes a controller to determine a user touch detection by a power adaptor coupled to the electronic device to operate the electronic device in an AC power mode. The power adaptor may comprise a proximity sensor to detect a user touch for detachment of the power adaptor from the electronic device, and a control circuit to operate a configuration pin in a low output mode to signal user touch detection. The controller may initiate central processing unit (CPU) throttling to reduce power consumption by the electronic device. The controller may further stop CPU throttling in response to detecting that the power adaptor has been detached from the electronic device. Further, the controller may switch the electronic device to a DC power mode to operate using DC power supplied by a battery of the electronic device in response to power adaptor detachment.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first nanostructure over the substrate. The first nanostructure has a (001) surface, the first nanostructure has a first channel direction on the (001) surface, and the first channel direction is [0 1 0] or [0 ?1 0]. The semiconductor device structure includes a gate stack surrounding the first nanostructure. The semiconductor device structure includes a first source/drain structure and a second source/drain structure over the substrate and over opposite sides of the gate stack. The first nanostructure is between the first source/drain structure and the second source/drain structure, and the first channel direction is from the first source/drain structure to the second source/drain structure.

Abstract: A semiconductor device includes a semiconductor substrate, an interfacial layer formed on the semiconductor substrate, a high-k dielectric layer formed on the interfacial layer, and a conductive gate electrode layer formed on the high-k dielectric layer. At least one of the high-k dielectric layer and the interfacial layer is doped with: a first dopant species, a second dopant species, and a third dopant species. The first dopant species and the second dopant species form a plurality of first dipole elements having a first polarity. The third dopant species forms a plurality of second dipole elements having a second polarity, and the first and second polarities are opposite.

Abstract: Described herein is a method for removing deposits off a surface of a chamber component. The method includes receiving a chamber component, and fixing the chamber component in a fixture. A slurry is then applied to a surface of the chamber component, where the slurry has a pH of about 5 to about 9. The surface is then polished using a polish pad and the slurry. The surface roughness of the surface after polishing is within about 10% of the surface roughness before polishing, and wherein deposits on the surface of the chamber component are removed by polishing. An alternative method for removing deposits is also presented, wherein the chamber component is heated to a temperature of about 500° C. to about 1500° C.

Abstract: A semiconductor device includes a channel layer, an interfacial layer, a gate dielectric layer, a gate electrode, dipole elements, and additional elements. The interfacial layer is disposed on the channel layer, and includes an insulating material. The gate dielectric layer is disposed over the interfacial layer such that the channel layer is separated from the gate dielectric layer by the interfacial layer. The gate electrode is disposed on the gate dielectric layer. The dipole elements are present in at least one of the interfacial layer and the gate dielectric layer in a predetermined amount such that the semiconductor device has a predetermined threshold voltage. The additional elements are located at a region where the dipole elements are present so as to reduce interfacial defects caused by the dipole elements. The additional elements are different from the dipole elements. Methods for manufacturing the semiconductor device are also disclosed.

Abstract: A method includes forming a fin structure including a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked over a substrate. A dummy gate structure is formed across the fin structure. The exposed second portions of the fin structure are removed. A selective etching process is performed, using a gas mixture including a hydrogen-containing gas and a fluorine-containing gas, to laterally recess the first semiconductor layers. Inner spacers are formed on opposite end surfaces of the laterally recessed first semiconductor layers. Source/drain epitaxial structures are formed on opposite end surfaces of the second semiconductor layers. The dummy gate structure is removed to expose the first portion of the fin structure. The laterally recessed first semiconductor layers are removed. A gate structure is formed to surround each of the second semiconductor layers.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first fin active region of a first semiconductor material disposed within the first region, oriented in a first direction, wherein the first fin active region has a <100> crystalline direction along the first direction; and a second fin active region of a second semiconductor material disposed within the second region and oriented in the first direction, wherein the second fin active region has a <110> crystalline direction along the first direction.

Abstract: An extrusion die (16) including a plurality of pins (38) having side surfaces defining an intersecting array of slots (30) extending axially into the die (16) from a discharge face (34) of the die (16). A plurality of feedholes (28) extend axially from an inlet face (32) of the die (16) opposite to the discharge face (34). The feedholes (28) connect with the slots (30) at intersections (35) within the die (16) to create a flow path from the inlet face (32) to the discharge face (34). A first coating (42) is on at least a portion of the feedholes (28) in a first zone (46) extending over a first axial length of the flow path. A second coating (44) that is different than the first coating (42) is on at least a portion of the side surfaces (37) of the pins (38) in a second zone (48) extending over a second axial length of the flow path. Methods of fabricating an extrusion die (16) and manufacturing a ceramic article (100), such as a honeycomb body, are also disclosed.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first nanostructure over the substrate. The first nanostructure has a first channel direction, and the first channel direction is [1 0 0], [?1 0 0], [0 1 0], or [0 ?1 0]. The semiconductor device structure includes a gate stack over the substrate and surrounding the first nanostructure. The semiconductor device structure includes a first source/drain structure and a second source/drain structure over the substrate and over opposite sides of the gate stack.

Abstract: A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The semiconductor device includes a substrate, a fin structure disposed on the substrate, a gate structure disposed on the fin structure, a source/drain (S/D) region disposed adjacent to the gate structure, a contact structure disposed on the S/D region, and a dipole layer disposed at an interface between the ternary compound layer and the S/D region. The contact structure includes a ternary compound layer disposed on the S/D region, a work function metal (WFM) silicide layer disposed on the ternary compound layer, and a contact plug disposed on the WFM silicide layer.