Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include a channel layer and a sacrificial layer. The method can further include forming a first recess structure in a first portion of the fin structure, forming a second recess structure in the sacrificial layer of a second portion of the fin structure, forming a dielectric layer in the first and second recess structures, and performing an oxygen-free cyclic etching process to etch the dielectric layer to expose the channel layer of the second portion of the fin structure. The oxygen-free cyclic etching process can include two etching processes to selectively etch the dielectric layer over the channel layer.

Abstract: A semiconductor device includes a first electrode layer, a ferroelectric layer, a first alignment layer and a second electrode layer. A material of the first alignment layer includes rare-earth metal oxide. The ferroelectric layer and the first alignment layer are disposed between the first electrode layer and the second electrode layer, and the first alignment layer is disposed between the ferroelectric layer and the first electrode layer.

Abstract: A method includes removing a first dummy gate stack and a second dummy gate stack to form a first trench and a second trench. The first dummy gate stack and the second dummy gate stack are in a first device region and a second device region, respectively. The method further includes depositing a first gate dielectric layer and a second gate dielectric layer extending into the first trench and the second trench, respectively, forming a fluorine-containing layer comprising a first portion over the first gate dielectric layer, and a second portion over the second gate dielectric layer, removing the second portion, performing an annealing process to diffuse fluorine in the first portion into the first gate dielectric layer, and at a time after the annealing process, forming a first work-function layer and a second work-function layer over the first gate dielectric layer and the second gate dielectric layer, respectively.

Abstract: Semiconductor devices and methods of forming the same are provided. A method includes providing a workpiece having a semiconductor structure; depositing a two-dimensional (2D) material layer over the semiconductor structure; forming a source feature and a drain feature electrically connected to the semiconductor structure and the 2D material layer, wherein the source feature and drain feature include a semiconductor material; and forming a gate structure over the two-dimensional material layer and interposed between the source feature and the drain feature. The gate structure, the source feature, the drain feature, the semiconductor structure and the 2D material layer are configured to form a field-effect transistor. The semiconductor structure and the 2D material layer function, respectively, as a first channel and a second channel between the source feature and the drain feature.

Abstract: The present disclosure relates to a desalination system of photovoltaic direct-driven membrane capacitive deionization. The system includes a photovoltaic direct-driven group and a municipal power grid-connected group. The photovoltaic direct-driven group includes a photovoltaic power collection unit, a power storage unit, a direct-driven power monitoring unit, a voltage adjustment unit, and a membrane capacitive deionization water purification unit. The municipal power grid-connected group includes a grid-connected control unit, a grid busbar unit, and an intelligent detection unit.

Abstract: A proposed Raman measurement device has a housing, an optical module, and a measuring probe. The measuring probe is connected to the optical module which is installed in the housing. A part of the measuring probe protrudes from the housing. An open end of the measuring probe outputs an emitted light from a laser light source in the optical module and receives the Raman scattered light excited from a surface to be detected. The axial centerline of the measuring probe and any parallel line in the length direction of the housing include an angle of 15° to 50° and the effective focusing distance between the open end of the measuring probe and the surface to be detected is 7 mm to 9 mm.

Abstract: A method includes removing a first dummy gate stack and a second dummy gate stack to form a first trench and a second trench. The first dummy gate stack and the second dummy gate stack are in a first device region and a second device region, respectively. The method further includes depositing a first gate dielectric layer and a second gate dielectric layer extending into the first trench and the second trench, respectively, forming a fluorine-containing layer comprising a first portion over the first gate dielectric layer, and a second portion over the second gate dielectric layer, removing the second portion, performing an annealing process to diffuse fluorine in the first portion into the first gate dielectric layer, and at a time after the annealing process, forming a first work-function layer and a second work-function layer over the first gate dielectric layer and the second gate dielectric layer, respectively.

Abstract: Embodiments of the present disclosure provide a video editing method and apparatus, an electronic device, and a storage medium. The method comprises: creating at least one editing subtask for a video editing task; in response to a first operation for triggering a target editing subtask, obtaining an initial video material and presenting an editing interface of the target editing subtask; recording the editing operation triggered in the editing interface and presenting an indication identifier of the editing operation in the editing track; generating an editing result of the target editing subtask based on the recorded information of the editing operation and the initial video material; based on the editing result of each editing subtask of the video editing task, generating a target video as an editing result of the video editing task.

Abstract: The present disclosure provides low resistance contacts and damascene interconnects with one or more graphene layers in fin structures of finFETs. An example semiconductor device can include a substrate with a fin structure that includes an epitaxial region. The semiconductor device can also include an etch stop layer on the epitaxial region, and an interlayer dielectric layer on the etch stop layer. The semiconductor device can further include a metal contact, above the epitaxial region, formed through the etch stop layer and the interlayer dielectric layer, and a graphene film at interfaces between the metal contact and each of the epitaxial region, the etch stop layer, and the interlayer dielectric layer.

Abstract: The problem of providing transistors that can be manufactured to any specified threshold voltage withing a broad range of threshold voltages without creating leakage, capacitance, or process compatibility issues is solved by introducing a buried layer of a second dielectric composition into a gate dielectric of a first dielectric composition. The second dielectric composition is selected relative to the first dielectric composition so that dipoles form around the interface of the two dielectrics. The dipoles create an electric field that causes a shift in the threshold voltage. The buried layer has a higher dielectric constant than the gate dielectric, is thinner than the gate dielectric, and is proximate the channel.

Abstract: A semiconductor device structure and methods of forming the same are described. In some embodiments, the structure includes an N-type source/drain epitaxial feature disposed over a substrate, a P-type source/drain epitaxial feature disposed over the substrate, a first silicide layer disposed directly on the N-type source/drain epitaxial feature, and a second silicide layer disposed directly on the P-type source/drain epitaxial feature. The first and second silicide layers include a first metal, and the second silicide layer is substantially thicker than the first silicide layer. The structure further includes a third silicide layer disposed directly on the first silicide layer and a fourth silicide layer disposed directly on the second silicide layer. The third and fourth silicide layer include a second metal different from the first metal, and the third silicide layer is substantially thicker than the fourth silicide layer.

Abstract: The present disclosure provides a phase-shifting assembly, including an antenna phase shifter and a drive apparatus. The antenna phase shifter includes at least one first phase-shifting fixed unit, at least one first phase-shifting movable unit, and at least one first phase-shifting rotation mechanism. The drive apparatus includes a power mechanism configured to provide a drive force to the antenna phase shifter, a first rotation member connected to the power mechanism and coupled to the at least one first phase-shifting rotation mechanism, and a position-limiting member configured to limit the movement of the first phase-shifting rotation mechanism in an axial direction of the first phase-shifting rotation mechanism. The first rotation member transfers the drive force of the power mechanism to the first phase-shifting rotation mechanism through the first rotation member to control a relative movement between a fixed phase-shifting trace and a first movable phase-shifting trace.

Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a channel member including a first channel layer and a second channel layer over the first channel layer, and a gate structure over the channel member. The first channel layer includes silicon, germanium, a III-V semiconductor, or a II-VI semiconductor and the second channel layer includes a two-dimensional material.

Abstract: The present disclosure provides low resistance contacts and damascene interconnects with one or more graphene layers in fin structures of FETs. An example semiconductor device can include a substrate with a fin structure that includes an epitaxial region. The semiconductor device can also include an etch stop layer on the epitaxial region, and an interlayer dielectric layer on the etch stop layer. The semiconductor device can further include a metal contact, above the epitaxial region, formed through the etch stop layer and the interlayer dielectric layer, and a graphene film at interfaces between the metal contact and each of the epitaxial region, the etch stop layer, and the interlayer dielectric layer.

Abstract: A honeycomb extrusion die (120) includes a die body (342) including an inlet face (315) and an outlet face (341). A plurality of pins (330) extend from the die body (342), wherein the pins (330) are arranged to define primary (312P) and secondary slots (312S). Primary slots (312P) include primary slot inlets (320P) and primary slot outlets (3120) and the secondary slots (312S) include secondary slot inlets (312SI) and secondary slot outlets (312SO). Feedholes (317) extend within the die body (342), the feedholes (317) including feedhole outlets (319), wherein the feedhole outlets (319) intersect only with the primary slot inlets (320P). First surface indentation features (345) extend into side surfaces (332) of the plurality of pins (330) defining the primary slots (312P). The first surface indentation features (345) are spaced from the primary slot outlets (3120). The secondary slots (312S) are devoid of surface indentation features. Other die bodies, extruders, and methods are disclosed.

Abstract: A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The semiconductor device includes first and second gate structures disposed on first and second fin structures, first and second source/drain (S/D) regions disposed on the first and second fin structures, first and second contact structures disposed on the first and second S/D regions, and a dipole layer disposed at an interface between the first nWFM silicide layer and the first S/D region. The first contact structure includes a first nWFM silicide layer disposed on the first S/D region and a first contact plug disposed on the first nWFM silicide layer. The second contact structure includes a pWFM silicide layer disposed on the second S/D region, a second nWFM silicide layer disposed on the pWFM silicide layer, and a second contact plug disposed on the pWFM silicide layer.

Abstract: Receiver circuitry for mitigating effects associated with the phase differences between a capture clock signal and the receipt of a data signal includes first data path circuitry, second data path circuitry, and phase alignment circuitry. The first data path circuitry receives a first data signal based on a capture clock signal. The second data path circuitry receives a second data signal based on the capture clock signal. The phase alignment circuitry adjusts the phase of a first launch clock signal and a second launch clock signal based on a first clock slip signal and a second clock slip signal, respectively. The phase alignment circuitry adjusts a phase of the capture clock signal relative to one of the first and the second launch clock signals based on a first adjustment value associated with the first data path circuitry and a second adjustment value associated with the second data path circuitry.

Abstract: A semiconductor structure includes a substrate and a semiconductor channel layer over the substrate. The semiconductor structure includes a high-k gate dielectric layer over the semiconductor channel layer, a work function metal layer over the high-k gate dielectric layer, and a bulk metal layer over the work function metal layer. The work function metal layer includes a first portion and a second portion over the first portion. Both the first portion and the second portion are conductive. Materials included in the second portion are also included in the first portion. The first portion is doped with silicon at a first dopant concentration, and the second portion is not doped with silicon or is doped with silicon at a second dopant concentration lower than the first dopant concentration.

Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a channel member including a first channel layer and a second channel layer over the first channel layer, and a gate structure over the channel member. The first channel layer includes silicon, germanium, a III-V semiconductor, or a II-VI semiconductor and the second channel layer includes a two-dimensional material.

Abstract: The present application relates to a video collection presentation method and apparatus, an electronic device, and a readable storage medium. The method comprises: presenting a plurality of first videos explaining video clipping skills in a video collection in a second page in the form of a directory, wherein when the video collection is presented by means of a directory, a subdirectory corresponding to the first videos comprises a plurality of directory items at different levels.