Patents by Inventor Min Shen
Min Shen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240372252Abstract: The present disclosure provides a phase-shifting assembly, including an antenna phase shifter and a drive apparatus. The antenna phase shifter includes at least one first phase-shifting fixed unit, at least one first phase-shifting movable unit, and at least one first phase-shifting rotation mechanism. The drive apparatus includes a power mechanism configured to provide a drive force to the antenna phase shifter, a first rotation member connected to the power mechanism and coupled to the at least one first phase-shifting rotation mechanism, and a position-limiting member configured to limit the movement of the first phase-shifting rotation mechanism in an axial direction of the first phase-shifting rotation mechanism. The first rotation member transfers the drive force of the power mechanism to the first phase-shifting rotation mechanism through the first rotation member to control a relative movement between a fixed phase-shifting trace and a first movable phase-shifting trace.Type: ApplicationFiled: July 17, 2024Publication date: November 7, 2024Inventors: Youfang HUANGFU, Suyang BAO, Min SHEN, Zhonghao ZOU
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Patent number: 12136570Abstract: The present disclosure provides low resistance contacts and damascene interconnects with one or more graphene layers in fin structures of FETs. An example semiconductor device can include a substrate with a fin structure that includes an epitaxial region. The semiconductor device can also include an etch stop layer on the epitaxial region, and an interlayer dielectric layer on the etch stop layer. The semiconductor device can further include a metal contact, above the epitaxial region, formed through the etch stop layer and the interlayer dielectric layer, and a graphene film at interfaces between the metal contact and each of the epitaxial region, the etch stop layer, and the interlayer dielectric layer.Type: GrantFiled: December 14, 2021Date of Patent: November 5, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Mrunal Abhijith Khaderbad, Wei-Yen Woon, Cheng-Ming Lin, Han-Yu Lin, Szu-Hua Chen, Jhih-Rong Huang, Tzer-Min Shen
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Patent number: 12109727Abstract: A honeycomb extrusion die (120) includes a die body (342) including an inlet face (315) and an outlet face (341). A plurality of pins (330) extend from the die body (342), wherein the pins (330) are arranged to define primary (312P) and secondary slots (312S). Primary slots (312P) include primary slot inlets (320P) and primary slot outlets (3120) and the secondary slots (312S) include secondary slot inlets (312SI) and secondary slot outlets (312SO). Feedholes (317) extend within the die body (342), the feedholes (317) including feedhole outlets (319), wherein the feedhole outlets (319) intersect only with the primary slot inlets (320P). First surface indentation features (345) extend into side surfaces (332) of the plurality of pins (330) defining the primary slots (312P). The first surface indentation features (345) are spaced from the primary slot outlets (3120). The secondary slots (312S) are devoid of surface indentation features. Other die bodies, extruders, and methods are disclosed.Type: GrantFiled: May 13, 2020Date of Patent: October 8, 2024Assignee: Corning IncorporatedInventors: Thomas William Brew, Thomas Mark Dubots, Kenneth Charles Sariego, Min Shen
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Publication number: 20240333270Abstract: Receiver circuitry for mitigating effects associated with the phase differences between a capture clock signal and the receipt of a data signal includes first data path circuitry, second data path circuitry, and phase alignment circuitry. The first data path circuitry receives a first data signal based on a capture clock signal. The second data path circuitry receives a second data signal based on the capture clock signal. The phase alignment circuitry adjusts the phase of a first launch clock signal and a second launch clock signal based on a first clock slip signal and a second clock slip signal, respectively. The phase alignment circuitry adjusts a phase of the capture clock signal relative to one of the first and the second launch clock signals based on a first adjustment value associated with the first data path circuitry and a second adjustment value associated with the second data path circuitry.Type: ApplicationFiled: March 30, 2023Publication date: October 3, 2024Inventors: Riyas Noorudeen REMLA, Showi-Min SHEN
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Publication number: 20240332393Abstract: A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The semiconductor device includes first and second gate structures disposed on first and second fin structures, first and second source/drain (S/D) regions disposed on the first and second fin structures, first and second contact structures disposed on the first and second S/D regions, and a dipole layer disposed at an interface between the first nWFM silicide layer and the first S/D region. The first contact structure includes a first nWFM silicide layer disposed on the first S/D region and a first contact plug disposed on the first nWFM silicide layer. The second contact structure includes a pWFM silicide layer disposed on the second S/D region, a second nWFM silicide layer disposed on the pWFM silicide layer, and a second contact plug disposed on the pWFM silicide layer.Type: ApplicationFiled: June 13, 2024Publication date: October 3, 2024Applicant: Taiwan Semiconductor Manufacturing Company, LTD.Inventors: Hsu-Kai CHANG, Jhih-Rong HUANG, Yen-Tien TUNG, Chia-Hung CHU, Shuen-Shin LIANG, Tzer-Min SHEN, Pinyen LIN, Sung-Li WANG
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Publication number: 20240313067Abstract: A semiconductor structure includes a substrate and a semiconductor channel layer over the substrate. The semiconductor structure includes a high-k gate dielectric layer over the semiconductor channel layer, a work function metal layer over the high-k gate dielectric layer, and a bulk metal layer over the work function metal layer. The work function metal layer includes a first portion and a second portion over the first portion. Both the first portion and the second portion are conductive. Materials included in the second portion are also included in the first portion. The first portion is doped with silicon at a first dopant concentration, and the second portion is not doped with silicon or is doped with silicon at a second dopant concentration lower than the first dopant concentration.Type: ApplicationFiled: May 20, 2024Publication date: September 19, 2024Inventors: Yen-Tien Tung, Szu-Wei Huang, Zhi-Ren Xiao, Yin-Chuan Chuang, Yung-Chien Huang, Kuan-Ting Liu, Tzer-Min Shen, Chung-Wei Wu, Zhiqiang Wu
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Patent number: 12087819Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a channel member including a first channel layer and a second channel layer over the first channel layer, and a gate structure over the channel member. The first channel layer includes silicon, germanium, a III-V semiconductor, or a II-VI semiconductor and the second channel layer includes a two-dimensional material.Type: GrantFiled: July 22, 2022Date of Patent: September 10, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Mrunal Abhijith Khaderbad, Dhanyakumar Mahaveer Sathaiya, Keng-Chu Lin, Tzer-Min Shen
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Publication number: 20240295950Abstract: The present application relates to a video collection presentation method and apparatus, an electronic device, and a readable storage medium. The method comprises: presenting a plurality of first videos explaining video clipping skills in a video collection in a second page in the form of a directory, wherein when the video collection is presented by means of a directory, a subdirectory corresponding to the first videos comprises a plurality of directory items at different levels.Type: ApplicationFiled: December 20, 2022Publication date: September 5, 2024Inventors: Shiting CHEN, Jiaxin WANG, Yijing LIN, Min SHEN
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Patent number: 12055498Abstract: A data processing method for detection of deterioration of semiconductor process kits includes the following steps: acquiring a plurality of Raman spectra data of a semiconductor process kit and performing a plurality calculating processes on the Raman spectra data to obtain a first deterioration state determining parameter indicating the aging degree of the entire semiconductor process kit and a second deterioration state determining parameter indicating the degree of variation of the internal molecular structure of the semiconductor process kit.Type: GrantFiled: June 28, 2021Date of Patent: August 6, 2024Assignee: TOP TECHNOLOGY PLATFORM CO., LTD.Inventors: Chyuan-Ruey Lin, Feng-Min Shen, Hung-Chia Su
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Patent number: 12040372Abstract: A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The semiconductor device includes first and second gate structures disposed on first and second fin structures, first and second source/drain (S/D) regions disposed on the first and second fin structures, first and second contact structures disposed on the first and second S/D regions, and a dipole layer disposed at an interface between the first nWFM silicide layer and the first S/D region. The first contact structure includes a first nWFM silicide layer disposed on the first S/D region and a first contact plug disposed on the first nWFM silicide layer. The second contact structure includes a pWFM silicide layer disposed on the second S/D region, a second nWFM silicide layer disposed on the pWFM silicide layer, and a second contact plug disposed on the pWFM silicide layer.Type: GrantFiled: August 10, 2022Date of Patent: July 16, 2024Assignee: Tawian Semiconductor Manufacturing Company, Ltd.Inventors: Hsu-Kai Chang, Jhih-Rong Huang, Yen-Tien Tung, Chia-Hung Chu, Shuen-Shin Liang, Tzer-Min Shen, Pinyen Lin, Sung-Li Wang
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Publication number: 20240233795Abstract: A memory circuit includes a plurality of memory cells, each memory cell of the plurality of memory cells including a gate electrode, a ferroelectric layer adjacent to the gate electrode, a channel layer adjacent to the ferroelectric layer, the channel layer including indium gallium zinc oxide (IGZO), and source and drain contacts adjacent to the channel layer opposite the ferroelectric layer. The memory circuit is configured to, during write operations to a memory cell of the plurality of memory cells, apply a plurality of voltage levels to the gate electrode relative to a ground voltage level applied to the source and drain contacts, a first voltage level of the plurality of voltage levels has a positive polarity and a first magnitude, and a second voltage level of the plurality of voltage levels has a negative polarity and a second magnitude greater than the first magnitude.Type: ApplicationFiled: March 25, 2024Publication date: July 11, 2024Inventors: Huan-Sheng WEI, Tzer-Min SHEN, Zhiqiang WU
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Publication number: 20240190043Abstract: A honeycomb extrusion die (120) with improved wear properties. Extrusion die has a die body (121) with inlet (122) and exit (123) faces, feedholes (124) with feedhole entrances (124A) and outlets (124B), and a plurality of die pins (126) having side surfaces (128) configured to define a matrix of intersecting slots (130). At least some of the intersecting slots and die pins define a slot structure with divots (132) formed in the side surfaces of the die pins between the feedholes and the exit face, entrance slot portions between the feedhole outlets and the divots, the entrance slot portions having an entrance slot width WA, and exit slot portions between the divots and the exit face, the exit slot portions having an exit slot width WB, wherein WA>WB over an entire slot length. Methods of manufacturing honeycomb structures using the honeycomb extrusion dies and of fabricating the extrusion dies are provided as are other aspects.Type: ApplicationFiled: May 18, 2022Publication date: June 13, 2024Inventors: Michael James Lehman, Min Shen
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Publication number: 20240178319Abstract: A semiconductor device includes a substrate, an interfacial layer formed on the semiconductor substrate, and a high-k dielectric layer formed on the interfacial layer. At least one of the high-k dielectric layer and the interfacial layer is doped with: a first dopant species, a second dopant species, and a third dopant species. The first dopant species and the second dopant species form a plurality of first dipole elements having a first polarity. The third dopant species forms a plurality of second dipole elements having a second polarity. A first concentration ratio of the first concentration of the first dopant species to the second concentration of the second dopant species of the p-type transistor is different from a second concentration ratio of the first concentration of the first dopant species to the second concentration of the second dopant species of the n-type transistor.Type: ApplicationFiled: February 2, 2024Publication date: May 30, 2024Inventors: Hsiang-Pi Chang, Yen-Tien Tung, Dawei Heh, Chung-Liang Cheng, I-Ming Chang, Yao-Sheng Huang, Tzer-Min Shen, Huang-Lin Chao
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Patent number: 11990522Abstract: A semiconductor structure includes a substrate and a semiconductor channel layer over the substrate. The semiconductor structure includes a high-k gate dielectric layer over the semiconductor channel layer, a work function metal layer over the high-k gate dielectric layer, and a bulk metal layer over the work function metal layer. The work function metal layer includes a first portion and a second portion over the first portion. Both the first portion and the second portion are conductive. Materials included in the second portion are also included in the first portion. The first portion is doped with silicon at a first dopant concentration, and the second portion is not doped with silicon or is doped with silicon at a second dopant concentration lower than the first dopant concentration.Type: GrantFiled: December 9, 2022Date of Patent: May 21, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yen-Tien Tung, Szu-Wei Huang, Zhi-Ren Xiao, Yin-Chuan Chuang, Yung-Chien Huang, Kuan-Ting Liu, Tzer-Min Shen, Chung-Wei Wu, Zhiqiang Wu
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Publication number: 20240153536Abstract: Embodiments of the present disclosure provide a video editing method and apparatus, an electronic device, and a storage medium. The method comprises: creating at least one editing subtask for a video editing task; in response to a first operation for triggering a target editing subtask, obtaining an initial video material and presenting an editing interface of the target editing subtask; recording the editing operation triggered in the editing interface and presenting an indication identifier of the editing operation in the editing track; generating an editing result of the target editing subtask based on the recorded information of the editing operation and the initial video material; based on the editing result of each editing subtask of the video editing task, generating a target video as an editing result of the video editing task.Type: ApplicationFiled: December 20, 2023Publication date: May 9, 2024Inventors: Xiaoran Zhang, Yuan Zhang, Xinyi Zha, Zhirui Jiang, Min Shen, Yu Zhang, Yan He, Jiahui Qiu, Shangshang Xiang, Long Ma
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Publication number: 20240123647Abstract: A fixture assembly for slitting a workpiece into a serpentine body, a cutting system having a fixture assembly, and a method of forming a serpentine body. The fixture assembly includes a patterned support section that has a plurality of support slats interspaced with gaps. A holder plate has an opening configured to receive the workpiece and positioned atop the patterned support section such that intended cutting locations in the workpiece are positioned directly above the gaps in the patterned support section and the slats are positioned directly below uncut portions of the serpentine body after cutting the workpiece.Type: ApplicationFiled: October 4, 2023Publication date: April 18, 2024Inventors: Song Lyu, Min Shen
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Patent number: 11942134Abstract: A memory circuit includes a memory array including a plurality of memory cells, each memory cell of the plurality of memory cells including an n-type channel layer including a metal oxide material, and a gate structure overlying and adjacent to the n-type channel layer, the gate structure including a conductive layer overlying a ferroelectric layer. The memory circuit is configured to apply a gate voltage to each memory cell of the plurality of memory cells in first and second write operations, the gate voltage has a positive polarity and a first magnitude in the first write operation and a negative polarity and a second magnitude greater than the first magnitude in the second write operation.Type: GrantFiled: November 18, 2022Date of Patent: March 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Huan-Sheng Wei, Tzer-Min Shen, Zhiqiang Wu
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Publication number: 20240097011Abstract: A method includes forming a fin structure over a substrate, wherein the fin structure comprises first semiconductor layers and second semiconductor layers alternately stacked over a substrate; forming a dummy gate structure over the fin structure; removing a portion of the fin structure uncovered by the dummy gate structure; performing a selective etching process to laterally recess the first semiconductor layers, including injecting a hydrogen-containing gas from a first gas source of a processing tool to the first semiconductor layers and the second semiconductor layers; and injecting an F2 gas from a second gas source of the processing tool to the first semiconductor layers and the second semiconductor layers; forming inner spacers on opposite end surfaces of the laterally recessed first semiconductor layers of the fin structure; and replacing the dummy gate structure and the first semiconductor layers with a metal gate structure.Type: ApplicationFiled: December 1, 2023Publication date: March 21, 2024Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY LIMITEDInventors: Han-Yu LIN, Fang-Wei LEE, Kai-Tak LAM, Raghunath PUTIKAM, Tzer-Min SHEN, Li-Te LIN, Pinyen LIN, Cheng-Tzu YANG, Tzu-Li LEE, Tze-Chung LIN
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Patent number: 11916471Abstract: An example electronic device includes a controller to determine a user touch detection by a power adaptor coupled to the electronic device to operate the electronic device in an AC power mode. The power adaptor may comprise a proximity sensor to detect a user touch for detachment of the power adaptor from the electronic device, and a control circuit to operate a configuration pin in a low output mode to signal user touch detection. The controller may initiate central processing unit (CPU) throttling to reduce power consumption by the electronic device. The controller may further stop CPU throttling in response to detecting that the power adaptor has been detached from the electronic device. Further, the controller may switch the electronic device to a DC power mode to operate using DC power supplied by a battery of the electronic device in response to power adaptor detachment.Type: GrantFiled: October 18, 2019Date of Patent: February 27, 2024Assignee: Hewlett-Packard Development Company, L.P.Inventors: Ting-Yang Tsai, Yi-Chen Chen, Ching-Lung Wang, Yu-Min Shen
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Publication number: 20240063263Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first nanostructure over the substrate. The first nanostructure has a (001) surface, the first nanostructure has a first channel direction on the (001) surface, and the first channel direction is [0 1 0] or [0 ?1 0]. The semiconductor device structure includes a gate stack surrounding the first nanostructure. The semiconductor device structure includes a first source/drain structure and a second source/drain structure over the substrate and over opposite sides of the gate stack. The first nanostructure is between the first source/drain structure and the second source/drain structure, and the first channel direction is from the first source/drain structure to the second source/drain structure.Type: ApplicationFiled: November 2, 2023Publication date: February 22, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Huang-Siang LAN, Sathaiya Mahaveer DHANYAKUMAR, Tzer-Min SHEN, Zhiqiang WU