Patents by Inventor Min-Soo Lim
Min-Soo Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11966342Abstract: A data processing system may be configured to include a memory device, a controller configured to access the memory device when a host requests offload processing of an application, and process the application, and a sharing memory management component within the controller and configured to: set controller owning rights of access to a target region of the memory device in response to the host stores, in the target region, data used for the requested offload processing of the application; and set the controller owning rights of access or the host owning rights of access to the target region based on a processing state of the application.Type: GrantFiled: August 1, 2022Date of Patent: April 23, 2024Assignee: SK hynix Inc.Inventor: Min Soo Lim
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Publication number: 20240099354Abstract: A system for manufacturing edible food products according to the present disclosure includes a first food ingredient supply apparatus configured to separate a single sheet of a first food ingredient from a first food ingredient stack including a plurality of stacked first food ingredients and supply the single sheet of first food ingredient, a second food ingredient supply apparatus configured to separate a single sheet of a second food ingredient from a second food ingredient stack including a plurality of stacked second food ingredients and supply the single sheet of second food ingredient, and a pressing device configured to form an edible food product by pressing a semi-finished product formed by seating the supplied single sheet of the first food ingredient on the supplied single sheet of the second food ingredient.Type: ApplicationFiled: December 28, 2021Publication date: March 28, 2024Applicant: CJ CHEILJEDANG CORPORATIONInventors: Duk Jin CHANG, Min Soo LIM, Seung Yong KIM, Yong Ho JEON, Sang Oh KIM, Myoung Il KWAK, Jong Hwa LEE
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Publication number: 20240101369Abstract: An apparatus for supplying food ingredients according to the present disclosure includes a food ingredient lifting part configured to separate and move upward a food ingredient stack from a food ingredient cassette on which food ingredients including a plurality of stacked food ingredients are seated, a food ingredient separation part configured to suck and move upward a single sheet of a food ingredient from the food ingredient stack moved upward by the food ingredient lifting part, and a horizontal movement part configured to transfer forward the single sheet of the food ingredient moved upward by the food ingredient separation part.Type: ApplicationFiled: December 28, 2021Publication date: March 28, 2024Applicant: CJ CHEILJEDANG CORPORATIONInventors: Duk Jin CHANG, Min Soo LIM, Seung Yong KIM, Yong Ho JEON, Sang Oh KIM, Myoung Il KWAK, Jong Hwa LEE
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Publication number: 20240083059Abstract: A cutting apparatus according to the present disclosure includes a cutting roller including a cutting body having a cylindrical shape and configured to rotate about an axis defined in a leftward/rightward direction, and cutting blades protruding outward in a radial direction of the cutting body further than a surface of the cutting body to cut an edible food product provided in a forward/rearward direction, and a cutting base part disposed at a position facing the cutting roller based on the edible food product to support the edible food product to be cut by the cutting roller.Type: ApplicationFiled: December 28, 2021Publication date: March 14, 2024Applicants: CJ CHEILJEDANG CORPORATION, CJ SEAFOOD CORPORATION, GREEN TECHNOLOGY CO., LTD.Inventors: Duk Jin CHANG, Min Soo LIM, Seung Yong KIM, Yong Ho JEON, Sang Oh KIM, Myoung Il KWAK, Jong Hwa LEE
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Publication number: 20240086135Abstract: An electronic device is provided that includes a first display and a second display. The electronic device also includes a processor configured to allocate a first set of resources to the first display and a second set of resources to the second display. The first set of resources is different from the second set of resources. Each of the first set of resources and the second set of resources includes one or more of at least one available hardware resource and at least one available software resource.Type: ApplicationFiled: November 13, 2023Publication date: March 14, 2024Inventors: Duk Ki HONG, Hyuk KANG, Jeong Hun KIM, Jae Bong YOO, Kyung Soo LIM, Jun Hak LIM, Min Gyew KIM, Na Jung Seo
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Patent number: 11925059Abstract: An organic light emitting diode display device includes a substrate having an emitting area and a non-emitting area. An insulating layer is on the substrate, and the insulating layer includes a plurality of convex portions, a plurality of connecting portions and at least one wall in the emitting area. A height of the at least one wall is greater than a height of the plurality of convex portions. A first electrode is on the substream, emitting layer is on the first electrode, a second electrode is on the emitting layer. The first electrode, the emitting layer and the second electrode constitute a light emitting diode.Type: GrantFiled: June 30, 2020Date of Patent: March 5, 2024Assignee: LG Display Co., Ltd.Inventors: Hyun-Soo Lim, Kang-Ju Lee, Soo-Kang Kim, Won-Hoe Koo, Min-Geun Choi
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Patent number: 11925057Abstract: Discussed is a display device for improving both transmittance and efficiency of light that is transmitted through a light-emitting unit and a transmissive unit due to a phase difference of ? at an interface between an organic layer and an optical compensation layer of the display device.Type: GrantFiled: December 17, 2021Date of Patent: March 5, 2024Assignee: LG DISPLAY CO., LTD.Inventors: Jae Hyeon Kim, Kwan Soo Kim, Young Nam Lim, Min Jee Kim, Seok Hyun Kim, Min Geun Song
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Patent number: 11917875Abstract: A display device includes a substrate including an active area having pixels and a non-active area including a pad region. A pad electrode is disposed in the pad region and includes a first pad electrode and a second pad electrode disposed on the first pad electrode. A first insulating pattern is interposed between the first and second pad electrodes. In a plan view, the first insulating pattern is positioned inside the first pad electrode, and a portion of the second pad electrode overlapping the first insulating pattern protrudes further from the substrate in a thickness direction than a portion of the second pad electrode not overlapping the first insulating pattern. The second pad electrode directly contacts a portion of the upper surface of the first pad electrode. In a plan view, an area of the second pad electrode is greater than an area of the first pad electrode.Type: GrantFiled: December 29, 2021Date of Patent: February 27, 2024Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Ki Kyung Youk, Chan Jae Park, Min Soo Kim, Yoon A Kim, Sang Duk Lee, Chel Gou Lim
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Publication number: 20230326500Abstract: A memory device includes a memory cell array and a peripheral circuit. The memory cell array includes a plurality of memory regions each identified by a row address and a column address. The peripheral circuit accesses the memory cell array by performing, based on an address, a burst length and a burst address gap provided from a memory controller, a burst operation supporting a variable burst address gap. The burst address gap is a numerical difference between adjacent column addresses, on which the burst operation is to be performed.Type: ApplicationFiled: June 12, 2023Publication date: October 12, 2023Inventors: Yong Sang PARK, Joo Young KIM, Min Soo LIM, Min Su PARK
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Patent number: 11699468Abstract: A memory device includes a memory cell array and a peripheral circuit. The memory cell array includes a plurality of memory regions each identified by a row address and a column address. The peripheral circuit accesses the memory cell array by performing, based on an address, a burst length and a burst address gap provided from a memory controller, a burst operation supporting a variable burst address gap. The burst address gap is a numerical difference between adjacent column addresses, on which the burst operation is to be performed.Type: GrantFiled: November 16, 2021Date of Patent: July 11, 2023Assignee: SK hynix Inc.Inventors: Yong Sang Park, Joo Young Kim, Min Soo Lim, Min Su Park
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Patent number: 11656765Abstract: A data bus inversion (DBI) circuit of a memory device includes a first processing component configured to generate first combination data by combining read data read from a memory cell region and previous data previously outputted from a data line, and generate second combination data by selectively inverting the first combination data depending on a result of comparing the first combination data and the previous data; and a second processing component configured to generate data to be outputted from the data line, by combining the second combination data and the previous data, wherein the second processing component generates bits of unnecessary bit positions in the data to be the same as bits of the unnecessary bit positions in the previous data.Type: GrantFiled: June 21, 2021Date of Patent: May 23, 2023Assignee: SK hynix Inc.Inventors: Yong Sang Park, Dae Woo Kim, Min Soo Lim, Young Duke Seo
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Publication number: 20220383916Abstract: A memory device includes a memory cell array and a peripheral circuit. The memory cell array includes a plurality of memory regions each identified by a row address and a column address. The peripheral circuit accesses the memory cell array by performing, based on an address, a burst length and a burst address gap provided from a memory controller, a burst operation supporting a variable burst address gap. The burst address gap is a numerical difference between adjacent column addresses, on which the burst operation is to be performed.Type: ApplicationFiled: November 16, 2021Publication date: December 1, 2022Inventors: Yong Sang PARK, Joo Young KIM, Min Soo LIM, Min Su PARK
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Publication number: 20220382687Abstract: A data processing system may be configured to include a memory device, a controller configured to access the memory device when a host requests offload processing of an application, and process the application, and a sharing memory management component within the controller and configured to: set controller owning rights of access to a target region of the memory device in response to the host stores, in the target region, data used for the requested offload processing of the application; and set the controller owning rights of access or the host owning rights of access to the target region based on a processing state of the application.Type: ApplicationFiled: August 1, 2022Publication date: December 1, 2022Inventor: Min Soo LIM
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Patent number: 11403236Abstract: A data processing system may be configured to include a memory device, a controller configured to access the memory device when a host requests offload processing of an application, and process the application, and a sharing memory management component within the controller and configured to: set controller owning rights of access to a target region of the memory device in response to the host stores, in the target region, data used for the requested offload processing of the application; and set the controller owning rights of access or the host owning rights of access to the target region based on a processing state of the application.Type: GrantFiled: August 18, 2020Date of Patent: August 2, 2022Assignee: SK hynix Inc.Inventor: Min Soo Lim
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Publication number: 20220214804Abstract: A data bus inversion (DBI) circuit of a memory device includes a first processing component configured to generate first combination data by combining read data read from a memory cell region and previous data previously outputted from a data line, and generate second combination data by selectively inverting the first combination data depending on a result of comparing the first combination data and the previous data; and a second processing component configured to generate data to be outputted from the data line, by combining the second combination data and the previous data, wherein the second processing component generates bits of unnecessary bit positions in the data to be the same as bits of the unnecessary bit positions in the previous data.Type: ApplicationFiled: June 21, 2021Publication date: July 7, 2022Inventors: Yong Sang PARK, Dae Woo KIM, Min Soo LIM, Young Duke SEO
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Patent number: 11327657Abstract: The present disclosure relates to a memory system and an operating method thereof. The memory system may include a shared memory device to store data, a sharing manager to store operation policy information and to autonomously generate a first internal command by using the operation policy information during an auto mode started in response to receiving an auto mode start command from a host, and a memory controller to generate a second internal command for controlling the shared memory device in response to the first internal command.Type: GrantFiled: May 22, 2020Date of Patent: May 10, 2022Assignee: SK hynix Inc.Inventor: Min Soo Lim
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Patent number: 11182099Abstract: A memory system includes a memory group including a plurality of memory devices having two or more different types; and a controller configured to control data input and output for the memory group, wherein the controller includes a scrubbing controller configured to collect health information to which a deterioration degree for each of the plurality of memory devices is reflected and determine a scrubbing interval for each of the plurality of memory devices based on the health information, the scrubbing interval being reduced in proportion to the deterioration degree.Type: GrantFiled: January 22, 2020Date of Patent: November 23, 2021Assignee: SK hynix Inc.Inventor: Min Soo Lim
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Publication number: 20210279185Abstract: A data processing system may be configured to include a memory device, a controller configured to access the memory device when a host requests offload processing of an application, and process the application, and a sharing memory management component within the controller and configured to: set controller owning rights of access to a target region of the memory device in response to the host stores, in the target region, data used for the requested offload processing of the application; and set the controller owning rights of access or the host owning rights of access to the target region based on a processing state of the application.Type: ApplicationFiled: August 18, 2020Publication date: September 9, 2021Inventor: Min Soo LIM
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Publication number: 20210026774Abstract: A data processing system may include a memory apparatus and a controller configured to control the memory apparatus. The memory apparatus includes a plurality of pages and is accessible in units of the pages. The controller may include a mode control component configured to generate an activation mode control signal for setting the memory apparatus in a partial page activation mode based on a type of a processing task requested by a host and address information requested to be accessed, and wherein less than all of a page of the memory apparatus being accessed is activated when the memory apparatus is in the partial page activation mode.Type: ApplicationFiled: February 26, 2020Publication date: January 28, 2021Inventor: Min Soo LIM
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Publication number: 20210011651Abstract: A memory system includes a memory group including a plurality of memory devices having two or more different types; and a controller configured to control data input and output for the memory group, wherein the controller includes a scrubbing controller configured to collect health information to which a deterioration degree for each of the plurality of memory devices is reflected and determine a scrubbing interval for each of the plurality of memory devices based on the health information, the scrubbing interval being reduced in proportion to the deterioration degree.Type: ApplicationFiled: January 22, 2020Publication date: January 14, 2021Inventor: Min Soo LIM