Abstract: A memory system includes a memory group including a plurality of memory devices having two or more different types; and a controller configured to control data input and output for the memory group, wherein the controller includes a scrubbing controller configured to collect health information to which a deterioration degree for each of the plurality of memory devices is reflected and determine a scrubbing interval for each of the plurality of memory devices based on the health information, the scrubbing interval being reduced in proportion to the deterioration degree.

Abstract: A data processing system may include a data processing group including a plurality of memory devices and a system controller configured to control a data input and output for the data processing group. The system controller may be configured to include a power management device configured to configure at least one memory group by grouping the plurality of memory devices based on a preset criterion and to determine a power mode of each of the memory groups based on whether a host device accesses each of the memory groups and an access interval.

Abstract: A data processing system may include a memory module composed of a plurality of memory banks including a plurality of pages; and a controller configured to control the memory module. The controller is configured to receive a type of an application of an operation to be offloaded and performed and a storage address of a program code of the application, to execute the program code, to store data generated as a result of the execution in the memory module, and to control, based on the type of the application, whether to refresh the memory module, a refresh cycle of the memory module, or both.

Abstract: The present disclosure relates to a memory system and an operating method thereof. The memory system may include a shared memory device to store data, a sharing manager to store operation policy information and to autonomously generate a first internal command by using the operation policy information during an auto mode started in response to receiving an auto mode start command from a host, and a memory controller to generate a second internal command for controlling the shared memory device in response to the first internal command.

Abstract: The present disclosure relates to a memory system and an operating method thereof. The memory system may include a shared memory device to store data, a sharing manager to store operation policy information and to autonomously generate a first internal command by using the operation policy information during an auto mode started in response to receiving an auto mode start command from a host, and a memory controller to generate a second internal command for controlling the shared memory device in response to the first internal command.

Abstract: The present disclosure relates to a memory system and an operating method thereof. The memory system may include a shared memory device to store data, a sharing manager to store operation policy information and to autonomously generate a first internal command by using the operation policy information during an auto mode started in response to receiving an auto mode start command from a host, and a memory controller to generate a second internal command for controlling the shared memory device in response to the first internal command.

Abstract: A memory controller includes a security key and parameter storage unit and a security engine. The security key and parameter storage unit stores at least one security key and at least one parameter that are used during encryption or decryption. The security engine receives encrypted data stored in an external boot memory, decrypts the received encrypted data by using the security key and the parameter, and outputs the decrypted data to a central processing unit (CPU), in a security operation mode.

Abstract: Multi-processor systems and methods thereof are provided. In an example, the multi-processor system may include a boot memory including a plurality of boot codes, each of the plurality of boot codes configured to facilitate an initialization process at one of a plurality of intellectual property (IP) blocks, each of the plurality of IP blocks having shared access to the boot memory. In another example, the multi-processor system may receive, from a first processor, a request to provide one of a plurality of boot codes from a boot memory, the received request sent in response to a system initializing signal, may read the requested boot code from the boot memory and may transfer, from a second processor, the read boot code to the first processor.

Abstract: Multi-processor systems and methods thereof are provided. In an example, the multi-processor system may include a boot memory including a plurality of boot codes, each of the plurality of boot codes configured to facilitate an initialization process at one of a plurality of intellectual property (IP) blocks, each of the plurality of IP blocks having shared access to the boot memory. In another example, the multi-processor system may receive, from a first processor, a request to provide one of a plurality of boot codes from a boot memory, the received request sent in response to a system initializing signal, may read the requested boot code from the boot memory and may transfer, from a second processor, the read boot code to the first processor.

Abstract: A processor apparatus capable of operating in a security mode includes a hash value storage unit and a security control unit including a plurality of access authentication hash values. The hash value storage value stores a plurality of hash values including a user authentication hash value and a plurality of access authentication hash values. The security control unit checks whether a boot code transmitted from a boot memory and a hash value from among the hash values, which corresponds to the boot code, are identical, and determines whether a boot operation and a debugging operation of the processor apparatus are allowed and whether an external user is allowed to have access to a predetermined intellectual property (IP) block. The processor apparatus can ensure debugging, security for the processor itself or security for a predetermined block included in the processor apparatus.

Abstract: Multi-processor systems and methods thereof are provided. In an example, the multi-processor system may include a boot memory including a plurality of boot codes, each of the plurality of boot codes configured to facilitate an initialization process at one of a plurality of intellectual property (IP) blocks, each of the plurality of IP blocks having shared access to the boot memory. In another example, the multi-processor system may receive, from a first processor, a request to provide one of a plurality of boot codes from a boot memory, the received request sent in response to a system initializing signal, may read the requested boot code from the boot memory and may transfer, from a second processor, the read boot code to the first processor.

Abstract: Multi-processor systems and methods thereof are provided. In an example, the multi-processor system may include a boot memory including a plurality of boot codes, each of the plurality of boot codes configured to facilitate an initialization process at one of a plurality of intellectual property (IP) blocks, each of the plurality of IP blocks having shared access to the boot memory. In another example, the multi-processor system may receive, from a first processor, a request to provide one of a plurality of boot codes from a boot memory, the received request sent in response to a system initializing signal, may read the requested boot code from the boot memory and may transfer, from a second processor, the read boot code to the first processor.

Abstract: A memory controller includes a security key and parameter storage unit and a security engine. The security key and parameter storage unit stores at least one security key and at least one parameter that are used during encryption or decryption. The security engine receives encrypted data stored in an external boot memory, decrypts the received encrypted data by using the security key and the parameter, and outputs the decrypted data to a central processing unit (CPU), in a security operation mode.

Abstract: A processor apparatus capable of operating in a security mode includes a hash value storage unit and a security control unit including a plurality of access authentication hash values. The hash value storage value stores a plurality of hash values including a user authentication hash value and a plurality of access authentication hash values. The security control unit checks whether a boot code transmitted from a boot memory and a hash value from among the hash values, which corresponds to the boot code, are identical, and determines whether a boot operation and a debugging operation of the processor apparatus are allowed and whether an external user is allowed to have access to a predetermined intellectual property (IP) block. The processor apparatus can ensure debugging, security for the processor itself or security for a predetermined block included in the processor apparatus.

Abstract: A slave device may be configured to receive at least one bus interface clock and bus interface signals from a bus coupled to the at least one bus interface unit. The slave device may also be configured to operate independently of at least one main function clock.

Abstract: Provided are a memory address generating circuit through which a user can freely select a method of generating an address of a memory according to an environment in which the memory is applied, and a memory controller including the memory address generating circuit. The memory address generating circuit includes a CAS address selecting circuit and an RAS address selecting circuit. The CAS address selecting circuit outputs a CAS address signal using N (N is an integer) column address signals and M (M is an integer) CAS address select signals. The RAS address selecting circuit which outputs an RAS address signal using K (K is an integer) row address signals and L (L is an integer) RAS address select signals. The memory address generating circuit controls the CAS address select signals and the RAS address select signals to perform a memory mapping most suitable for a system in which the memory is used.

Abstract: Multi-processor systems and methods thereof are provided. In an example, the multi-processor system may include a boot memory including a plurality of boot codes, each of the plurality of boot codes configured to facilitate an initialization process at one of a plurality of intellectual property (IP) blocks, each of the plurality of IP blocks having shared access to the boot memory. In another example, the multi-processor system may receive, from a first processor, a request to provide one of a plurality of boot codes from a boot memory, the received request sent in response to a system initializing signal, may read the requested boot code from the boot memory and may transfer, from a second processor, the read boot code to the first processor.

Abstract: Provided are a memory address generating circuit through which a user can freely select a method of generating an address of a memory according to an environment in which the memory is applied, and a memory controller including the memory address generating circuit. The memory address generating circuit includes a CAS address selecting circuit and an RAS address selecting circuit. The CAS address selecting circuit outputs a CAS address signal using N (N is an integer) column address signals and M (M is an integer) CAS address select signals. The RAS address selecting circuit which outputs an RAS address signal using K (K is an integer) row address signals and L (L is an integer) RAS address select signals. The memory address generating circuit controls the CAS address select signals and the RAS address select signals to perform a memory mapping most suitable for a system in which the memory is used.

Abstract: A slave device may be configured to receive at least one bus interface clock and bus interface signals from a bus coupled to the at least one bus interface unit.