Abstract: A composition for solar cell electrodes includes a silver powder; a glass frit; and an organic vehicle, wherein the glass frit includes bismuth (Bi), tellurium (Te), and chromium (Cr).

Abstract: A composition for solar cell electrodes includes a silver powder; a glass frit; and an organic vehicle, wherein the glass frit includes bismuth (Bi), tellurium (Te), and chromium (Cr).

Abstract: The present disclosure relates to an apparatus for transmitting a position of a multi-axis transport system and a method thereof, and provides an apparatus for transmitting a position of a multi-axis transport system capable of providing an accurately detected position of a nondestructive system to a user by converting a sensor signal for measuring a position of the multi-axis transport system into position information (x, y, and z coordinates) which may be matched to the detected position of the nondestructive system and then transmitting the converted position information to the nondestructive system via high speed communication (e.g., Local Area Network (LAN) or Peripheral component Interconnect (PCI)), and a method thereof.

Abstract: A composition for solar cell electrodes includes a silver powder; a glass frit; and an organic vehicle, wherein the glass frit includes bismuth (Bi), tellurium (Te), and chromium (Cr).

Abstract: A control method of a mobile terminal is disclosed. The control method of a mobile terminal includes: acquiring a pressure signal through a pressure sensing module for sensing a change in pressure applied to at least one part of the body in at least two degrees; and generating an event for changing a display state of a display unit through a control signal to be matched to the pressure signal. Emotional quality can be improved by changing a display state of a display unit in response to a change in pressure applied to the body.

Abstract: A method for manufacturing an electrode for a display apparatus includes printing and drying a conductive paste on a substrate, and printing a glass paste on the dried conductive paste, followed by patterning.

Abstract: A semiconductor device includes: a second conductive layer formed over a first conductive layer; and a dummy conductive layer formed between the first and second conductive layers with through-holes formed therein. The first and second conductive layers include signal lines electrically coupled to each other through signal metal contacts passing through the through-holes, and the second conductive layer includes power lines electrically coupled to the dummy conductive layer through power metal contacts.

Abstract: A lighting apparatus is disclosed. The lighting apparatus is capable of achieving improved aesthetics by irradiating mood lighting into a storage container and also, of functioning to display a variety of status information about the storage container to the outside and to sterilize the interior of the storage container.

Abstract: A semiconductor device having a power tracking circuit configured for activating a power tracking signal for a period corresponding to a period during which an external voltage retains a level lower than a level of a low power mode reference voltage if the external voltage retains the level lower than the level of the low power mode reference voltage for at least a preselected time.

Abstract: A test mode signal generation circuit includes a pre-decoder block configured to output first and second control signals and test address signals in response to first and second address signals, and a signal generation block configured to decode the test address signals in response to the first control signal and generate first and second test mode group signals each including a plurality of test mode signals.

Abstract: A delay locked loop (DLL) circuit includes a timing pulse generating unit configured to generate a plurality of timing pulses, which are sequentially pulsed during delay shifting update periods, in response to a source clock, wherein the number of the generated timing pulses changes according to a frequency of the source clock; a clock delay unit configured to compare a phase of the source clock with a phase of a feedback clock at a time point defined by each of the timing pulses, and delay a phase of an internal clock, corresponding to a rising or falling edge of the source clock, according to the comparison result; and a delay replica modeling unit configured to reflect actual delay conditions of the internal clock path on an output clock of the clock delay unit, and to output the feedback clock.

Abstract: A control method of a mobile terminal is disclosed. The control method of a mobile terminal includes: acquiring a pressure signal through a pressure sensing module for sensing a change in pressure applied to at least one part of the body in at least two degrees; and generating an event for changing a display state of a display unit through a control signal to be matched to the pressure signal. Emotional quality can be improved by changing a display state of a display unit in response to a change in pressure applied to the body.

Abstract: A method for manufacturing an electrode for a display apparatus includes printing and drying a conductive paste on a substrate, and printing a glass paste on the dried conductive paste, followed by patterning.

Abstract: A rod-shaped FRP bar is manufactured with a fiber and a resin by using a nozzle (100) which includes an outer nozzle (11) having a penetration hole at its center and a plurality of middle nozzles (12) disposed at an inlet of the outer nozzle 11 so that one middle nozzle is located inside another middle nozzle with an interval. Fibers are supplied through a center hole of the middle nozzle located at an innermost location, through intervals between the middle nozzles and through intervals between the middle nozzles and the outer nozzle, thereby making a hybrid FRP bar (1) having a section in which the fibers configure a plurality of fiber distribution layers from the center of the FRP bar toward the outside.

Abstract: A semiconductor memory device includes a memory bank having a first cell block including a plurality of memory cells coupled to a first word line which can be activated in response to a row address signal, a second cell block including a plurality of memory cells coupled to a second word line, and a dummy cell block including a plurality of memory cells coupled to a third word line which can be activated in response to the row address signal. The first and second cell blocks share a first sense amplifier. The second cell block and the dummy cell block share a second sense amplifier. The first cell block is disposed adjacent to a first edge of the memory bank, and the dummy cell block is disposed adjacent to a second edge of the memory bank opposing the first edge.

Abstract: A semiconductor device having a power tracking circuit configured for activating a power tracking signal for a period corresponding to a period during which an external voltage retains a level lower than a level of a low power mode reference voltage if the external voltage retains the level lower than the level of the low power mode reference voltage for at least a preselected time.

Abstract: A test mode signal generation circuit includes a pre-decoder block configured to output first and second control signals and test address signals in response to first and second address signals, and a signal generation block configured to decode the test address signals in response to the first control signal and generate first and second test mode group signals each including a plurality of test mode signals.

Abstract: A rear panel for a plasma display panel (PDP) includes a substrate, and an address electrode on the substrate, the address electrode including an aluminum containing layer and a silver containing layer stacked on each other.

Abstract: A latency control circuit of a semiconductor device includes a phase detection unit configured to generate phase information regarding a phase difference between an external clock and an internal clock, a delay amount deciding unit configured to decide a latency delay amount based on path information of an input signal, a latency value of the input signal, and the phase information, and a latency delay unit configured to generate a latency signal by delaying the input signal according to the latency delay amount and the phase information to produce a delayed input signal and by synchronizing the delayed input signal with the internal clock.

Abstract: A latency control circuit of a semiconductor device includes a phase detection unit configured to generate phase information regarding a phase difference between an external clock and an internal clock, a delay amount deciding unit configured to decide a latency delay amount based on path information of an input signal, a latency value of the input signal, and the phase information, and a latency delay unit configured to generate a latency signal by delaying the input signal according to the latency delay amount and the phase information to produce a delayed input signal and by synchronizing the delayed input signal with the internal clock.